| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/ |
| i915_batch.h | 36 #define OUT_BATCH(dword) i915_winsys_batchbuffer_dword(i915->batch, dword)
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/ |
| i915_batch.h | 38 #define OUT_BATCH(dword) \
|
| /xsrc/external/mit/xf86-video-intel/dist/xvmc/ |
| intel_batchbuffer.h | 17 #define OUT_BATCH(n) \
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/ |
| intel_batchbuffer.h | 17 #define OUT_BATCH(n) \
|
| /xsrc/external/mit/xf86-video-intel-old/dist/src/xvmc/ |
| intel_batchbuffer.h | 19 #define OUT_BATCH(n) \
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/ |
| radeon_cmdbuf.h | 39 #define OUT_BATCH(data) \
70 * The number of (direct or indirect) OUT_BATCH calls between the previous
89 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
90 OUT_BATCH((val))
95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/ |
| radeon_cmdbuf.h | 39 #define OUT_BATCH(data) \
70 * The number of (direct or indirect) OUT_BATCH calls between the previous
89 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
90 OUT_BATCH((val))
95 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/ |
| intel_batchbuffer.h | 137 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel, d)
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/ |
| brw_batch.h | 138 #define OUT_BATCH(d) *__map++ = (d)
139 #define OUT_BATCH_F(f) OUT_BATCH(float_as_int((f)))
145 OUT_BATCH(reloc); \
153 OUT_BATCH(reloc64); \
154 OUT_BATCH(reloc64 >> 32); \
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/ |
| intel_batchbuffer.h | 137 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel, d)
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/ |
| intel_batchbuffer.h | 137 #define OUT_BATCH(d) *__map++ = (d)
138 #define OUT_BATCH_F(f) OUT_BATCH(float_as_int((f)))
144 OUT_BATCH(reloc); \
152 OUT_BATCH(reloc64); \
153 OUT_BATCH(reloc64 >> 32); \
|
| /xsrc/external/mit/xf86-video-intel-old/dist/src/ |
| i830_batchbuffer.h | 117 #define OUT_BATCH(dword) intel_batch_emit_dword(pI830, dword)
133 OUT_BATCH(tmp.ui); \
|
| /xsrc/external/mit/xf86-video-intel/dist/src/uxa/ |
| intel_batchbuffer.h | 162 #define OUT_BATCH(dword) intel_batch_emit_dword(intel, dword)
184 OUT_BATCH(tmp.ui); \
211 OUT_BATCH(MI_FLUSH_DW); \
212 OUT_BATCH(0); \
213 OUT_BATCH(0); \
214 OUT_BATCH(0); \
215 OUT_BATCH(MI_LOAD_REGISTER_IMM); \
216 OUT_BATCH(BCS_SWCTRL); \
217 OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 | \
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/ |
| intel_batchbuffer.h | 162 #define OUT_BATCH(dword) intel_batch_emit_dword(intel, dword)
184 OUT_BATCH(tmp.ui); \
|
| /xsrc/external/mit/xf86-video-intel/dist/src/sna/ |
| gen4_render.c | 224 #define OUT_BATCH(v) batch_emit(sna, v)
272 OUT_BATCH(GEN4_3DPRIMITIVE |
277 OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start);
278 OUT_BATCH(sna->render.vertex_start);
279 OUT_BATCH(1); /* single instance */
280 OUT_BATCH(0); /* start instance location */
281 OUT_BATCH(0); /* index buffer offset, ignored */
599 OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | 3);
600 OUT_BATCH((id << VB0_BUFFER_INDEX_SHIFT) | VB0_VERTEXDATA |
604 OUT_BATCH(0)
[all...] |
| gen5_render.c | 214 #define OUT_BATCH(v) batch_emit(sna, v)
261 OUT_BATCH(GEN5_3DPRIMITIVE |
266 OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start);
267 OUT_BATCH(sna->render.vertex_start);
268 OUT_BATCH(1); /* single instance */
269 OUT_BATCH(0); /* start instance location */
270 OUT_BATCH(0); /* index buffer offset, ignored */
585 OUT_BATCH(GEN5_3DSTATE_VERTEX_BUFFERS | 3);
586 OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT | VB0_VERTEXDATA |
590 OUT_BATCH(0)
[all...] |
| gen6_render.c | 240 #define OUT_BATCH(v) batch_emit(sna, v)
441 OUT_BATCH(GEN6_PIPE_CONTROL | (4 - 2));
442 OUT_BATCH(GEN6_PIPE_CONTROL_WC_FLUSH |
445 OUT_BATCH(0);
446 OUT_BATCH(0);
458 OUT_BATCH(GEN6_PIPE_CONTROL | (4 - 2));
459 OUT_BATCH(GEN6_PIPE_CONTROL_WC_FLUSH | stall);
460 OUT_BATCH(0);
461 OUT_BATCH(0);
467 OUT_BATCH(GEN6_PIPE_CONTROL | (4 - 2))
[all...] |
| gen3_render.c | 65 #define OUT_BATCH(v) batch_emit(sna, v)
1897 OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | IAB_MODIFY_ENABLE |
1902 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
1912 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | I1_LOAD_S(6) | 3);
1913 OUT_BATCH(0); /* Disable texture coordinate wrap-shortest */
1914 OUT_BATCH((1 << S4_POINT_WIDTH_SHIFT) |
1918 OUT_BATCH(0); /* Disable fog/stencil. *Enable* write mask. */
1919 OUT_BATCH(S6_COLOR_WRITE_ONLY); /* Disable blending, depth */
1921 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
1922 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE)
[all...] |
| gen7_render.c | 338 #define OUT_BATCH(v) batch_emit(sna, v)
539 OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
540 OUT_BATCH(sna->render_state.gen7.info->urb.push_ps_size);
543 OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2));
544 OUT_BATCH((sna->render_state.gen7.info->urb.max_vs_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
548 OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2));
549 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
552 OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2));
553 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
556 OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2))
[all...] |
| gen8_render.c | 242 #define OUT_BATCH(v) batch_emit(sna, v)
509 OUT_BATCH(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS | (2 - 2));
510 OUT_BATCH(0);
512 OUT_BATCH(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS | (2 - 2));
513 OUT_BATCH(0);
515 OUT_BATCH(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS | (2 - 2));
516 OUT_BATCH(0);
518 OUT_BATCH(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS | (2 - 2));
519 OUT_BATCH(0);
521 OUT_BATCH(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2))
[all...] |
| gen9_render.c | 258 #define OUT_BATCH(v) batch_emit(sna, v)
560 OUT_BATCH(GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS | (2 - 2));
561 OUT_BATCH(0);
563 OUT_BATCH(GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS | (2 - 2));
564 OUT_BATCH(0);
566 OUT_BATCH(GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS | (2 - 2));
567 OUT_BATCH(0);
569 OUT_BATCH(GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS | (2 - 2));
570 OUT_BATCH(0);
572 OUT_BATCH(GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2))
[all...] |
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/ |
| gen4_render.c | 187 #define OUT_BATCH(v) batch_emit(sna, v)
235 OUT_BATCH(GEN4_3DPRIMITIVE |
240 OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start);
241 OUT_BATCH(sna->render.vertex_start);
242 OUT_BATCH(1); /* single instance */
243 OUT_BATCH(0); /* start instance location */
244 OUT_BATCH(0); /* index buffer offset, ignored */
562 OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | 3);
563 OUT_BATCH((id << VB0_BUFFER_INDEX_SHIFT) | VB0_VERTEXDATA |
567 OUT_BATCH(0)
[all...] |
| gen5_render.c | 177 #define OUT_BATCH(v) batch_emit(sna, v)
224 OUT_BATCH(GEN5_3DPRIMITIVE |
229 OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start);
230 OUT_BATCH(sna->render.vertex_start);
231 OUT_BATCH(1); /* single instance */
232 OUT_BATCH(0); /* start instance location */
233 OUT_BATCH(0); /* index buffer offset, ignored */
548 OUT_BATCH(GEN5_3DSTATE_VERTEX_BUFFERS | 3);
549 OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT | VB0_VERTEXDATA |
553 OUT_BATCH(0)
[all...] |
| gen6_render.c | 206 #define OUT_BATCH(v) batch_emit(sna, v)
407 OUT_BATCH(GEN6_PIPE_CONTROL | (4 - 2));
408 OUT_BATCH(GEN6_PIPE_CONTROL_WC_FLUSH |
411 OUT_BATCH(0);
412 OUT_BATCH(0);
424 OUT_BATCH(GEN6_PIPE_CONTROL | (4 - 2));
425 OUT_BATCH(GEN6_PIPE_CONTROL_WC_FLUSH | stall);
426 OUT_BATCH(0);
427 OUT_BATCH(0);
433 OUT_BATCH(GEN6_PIPE_CONTROL | (4 - 2))
[all...] |
| gen8_render.c | 203 #define OUT_BATCH(v) batch_emit(sna, v)
443 OUT_BATCH(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS | (2 - 2));
444 OUT_BATCH(0);
446 OUT_BATCH(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS | (2 - 2));
447 OUT_BATCH(0);
449 OUT_BATCH(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS | (2 - 2));
450 OUT_BATCH(0);
452 OUT_BATCH(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS | (2 - 2));
453 OUT_BATCH(0);
455 OUT_BATCH(GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2))
[all...] |
