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    Searched defs:brw (Results 1 - 25 of 151) sorted by relevancy

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  /xsrc/external/mit/MesaLib/dist/src/intel/compiler/
brw_vec4_surface_builder.h 30 namespace brw { namespace
brw_vec4_tes.h 36 namespace brw { namespace
64 } /* namespace brw */
brw_vec4_vs.h 29 namespace brw { namespace
58 } /* namespace brw */
brw_vec4_tcs.h 37 namespace brw { namespace
81 } /* namespace brw */
brw_ir_performance.h 30 namespace brw { namespace
brw_vec4_gs_nir.cpp 26 namespace brw { namespace
brw_vec4_gs_visitor.h 38 namespace brw { namespace
76 } /* namespace brw */
brw_vec4_vs_visitor.cpp 28 namespace brw { namespace
117 } /* namespace brw */
  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
brw_buffers.c 39 struct brw_context *const brw = brw_context(ctx); local
45 if (brw->driContext->driDrawablePriv)
46 dri2InvalidateDrawable(brw->driContext->driDrawablePriv);
47 brw_prepare_render(brw);
56 struct brw_context *const brw = brw_context(ctx); local
62 if (brw->driContext->driDrawablePriv)
63 dri2InvalidateDrawable(brw->driContext->driReadablePriv);
64 brw_prepare_render(brw);
brw_extensions.c 39 struct brw_context *brw = brw_context(ctx); local
40 const struct intel_device_info *devinfo = &brw->screen->devinfo;
147 else if (devinfo->is_haswell && can_do_pipelined_register_writes(brw->screen))
149 else if (devinfo->ver >= 7 && can_do_pipelined_register_writes(brw->screen))
182 !driQueryOptionb(&brw->screen->optionCache, "disable_blend_func_extended");
219 ctx->Extensions.ARB_timer_query = brw->screen->hw_has_timestamp;
235 brw->predicate.supported = false;
264 if (can_do_pipelined_register_writes(brw->screen)) {
270 if (can_do_compute_dispatch(brw->screen) &&
279 if (can_do_predicate_writes(brw->screen))
    [all...]
brw_reset.c 37 struct brw_context *brw = brw_context(ctx); local
38 struct drm_i915_reset_stats stats = { .ctx_id = brw->hw_ctx };
44 assert(brw->hw_ctx != 0);
50 if (brw->reset_count != 0)
53 if (drmIoctl(brw->screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats) != 0)
60 brw->reset_count = stats.reset_count;
69 brw->reset_count = stats.reset_count;
77 brw_check_for_reset(struct brw_context *brw)
79 struct drm_i915_reset_stats stats = { .ctx_id = brw->hw_ctx };
81 if (drmIoctl(brw->screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats) != 0
    [all...]
brw_tex_copy.c 53 struct brw_context *brw = brw_context(ctx); local
56 if (brw_blorp_copytexsubimage(brw, rb, texImage, slice, x, y,
brw_formatquery.c 34 struct brw_context *brw = brw_context(ctx); local
35 const struct intel_device_info *devinfo = &brw->screen->devinfo;
gfx7_sol_state.c 42 struct brw_context *brw = brw_context(ctx); local
46 assert(brw->screen->devinfo.ver == 7);
49 brw_save_primitives_written_counters(brw, brw_obj);
52 if (!can_do_pipelined_register_writes(brw->screen)) {
53 brw_batch_flush(brw);
54 brw->batch.needs_sol_reset = true;
57 brw_load_register_imm32(brw, GFX7_SO_WRITE_OFFSET(i), 0);
74 struct brw_context *brw = brw_context(ctx); local
80 brw_save_primitives_written_counters(brw, brw_obj);
102 struct brw_context *brw = brw_context(ctx) local
132 struct brw_context *brw = brw_context(ctx); local
    [all...]
brw_copy_image.c 38 copy_miptrees(struct brw_context *brw,
45 const struct intel_device_info *devinfo = &brw->screen->devinfo;
55 if (brw_miptree_copy(brw, src_mt, src_level, src_z, src_x, src_y,
61 brw_blorp_copy_miptrees(brw,
78 struct brw_context *brw = brw_context(ctx); local
115 copy_miptrees(brw, src_mt, src_x, src_y, src_z, src_level,
129 copy_miptrees(brw, src_mt->stencil_mt, src_x, src_y, src_z, src_level,
  /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
brw_vec4_surface_builder.h 30 namespace brw { namespace
brw_vec4_tes.h 36 namespace brw { namespace
63 } /* namespace brw */
brw_vec4_vs.h 29 namespace brw { namespace
59 } /* namespace brw */
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
intel_buffers.c 39 struct brw_context *const brw = brw_context(ctx); local
45 dri2InvalidateDrawable(brw->driContext->driDrawablePriv);
46 intel_prepare_render(brw);
55 struct brw_context *const brw = brw_context(ctx); local
61 dri2InvalidateDrawable(brw->driContext->driReadablePriv);
62 intel_prepare_render(brw);
intel_extensions.c 39 struct brw_context *brw = brw_context(ctx); local
40 const struct gen_device_info *devinfo = &brw->screen->devinfo;
147 else if (devinfo->is_haswell && can_do_pipelined_register_writes(brw->screen))
149 else if (devinfo->gen >= 7 && can_do_pipelined_register_writes(brw->screen))
182 !driQueryOptionb(&brw->optionCache, "disable_blend_func_extended");
215 ctx->Extensions.ARB_timer_query = brw->screen->hw_has_timestamp;
229 brw->predicate.supported = false;
258 if (can_do_pipelined_register_writes(brw->screen)) {
264 if (can_do_compute_dispatch(brw->screen) &&
272 if (can_do_predicate_writes(brw->screen))
    [all...]
intel_tex_copy.c 53 struct brw_context *brw = brw_context(ctx); local
56 if (brw_blorp_copytexsubimage(brw, rb, texImage, slice, x, y,
brw_primitive_restart.c 82 struct brw_context *brw = brw_context(ctx); local
83 const struct gen_device_info *devinfo = &brw->screen->devinfo;
136 struct brw_context *brw = brw_context(ctx); local
146 if (brw->prim_restart.in_progress) {
160 brw->prim_restart.in_progress = true;
165 brw->prim_restart.enable_cut_index = true;
168 brw->prim_restart.enable_cut_index = false;
176 brw->prim_restart.in_progress = false;
brw_reset.c 37 struct brw_context *brw = brw_context(ctx); local
38 __DRIscreen *dri_screen = brw->screen->driScrnPriv;
39 struct drm_i915_reset_stats stats = { .ctx_id = brw->hw_ctx };
45 assert(brw->hw_ctx != 0);
51 if (brw->reset_count != 0)
61 brw->reset_count = stats.reset_count;
70 brw->reset_count = stats.reset_count;
78 brw_check_for_reset(struct brw_context *brw)
80 __DRIscreen *dri_screen = brw->screen->driScrnPriv;
81 struct drm_i915_reset_stats stats = { .ctx_id = brw->hw_ctx }
    [all...]
brw_formatquery.c 34 struct brw_context *brw = brw_context(ctx); local
35 const struct gen_device_info *devinfo = &brw->screen->devinfo;
gen7_sol_state.c 42 struct brw_context *brw = brw_context(ctx); local
46 assert(brw->screen->devinfo.gen == 7);
49 brw_save_primitives_written_counters(brw, brw_obj);
52 if (!can_do_pipelined_register_writes(brw->screen)) {
53 intel_batchbuffer_flush(brw);
54 brw->batch.needs_sol_reset = true;
57 brw_load_register_imm32(brw, GEN7_SO_WRITE_OFFSET(i), 0);
74 struct brw_context *brw = brw_context(ctx); local
80 brw_save_primitives_written_counters(brw, brw_obj);
102 struct brw_context *brw = brw_context(ctx) local
132 struct brw_context *brw = brw_context(ctx); local
    [all...]

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