| /src/sys/arch/arm/imx/ |
| imx31_clock.c | 117 struct imx31_clocks clk; local in function:imxclock_get_timerfreq
118 imx31_get_clocks(&clk);
120 return clk.ipg_clk;
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| gt215.h | 9 u32 clk; member in struct:gt215_clk_info
|
| /src/sys/dev/fdt/ |
| dwcwdt_fdt.c | 65 struct clk *clk; local in function:dwcwdt_fdt_attach
74 clk = fdtbus_clock_get_index(phandle, 0);
75 if (clk == NULL || clk_enable(clk) != 0) {
95 sc->sc_clkrate = clk_get_rate(clk);
|
| ahcisata_fdt.c | 65 struct clk *clk; local in function:ahcisata_fdt_attach
92 for (i = 0; (clk = fdtbus_clock_get_index(phandle, i)) != NULL; i++)
93 if (clk_enable(clk) != 0) {
|
| ehci_fdt.c | 76 struct clk *clk; local in function:ehci_fdt_attach
90 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)
91 if (clk_enable(clk) != 0) {
|
| ohci_fdt.c | 76 struct clk *clk; local in function:ohci_fdt_attach
90 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)
91 if (clk_enable(clk) != 0) {
|
| dwiic_fdt.c | 93 struct clk *clk; local in function:dwiic_fdt_attach
95 for (c = 0; (clk = fdtbus_clock_get_index(phandle, c)) != NULL; c++) {
96 if (clk_enable(clk) != 0) {
|
| /src/sys/arch/arm/amlogic/ |
| meson_rng.c | 77 struct clk *clk; local in function:meson_rng_attach
94 clk = fdtbus_clock_get(phandle, "core");
95 if (clk != NULL && clk_enable(clk) != 0) {
|
| /src/sys/arch/arm/fdt/ |
| aaci_fdt.c | 68 struct clk *clk; local in function:aaci_fdt_attach
83 for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++)
84 if (clk_enable(clk) != 0) {
|
| plkmi_fdt.c | 68 struct clk *clk; local in function:plkmi_fdt_attach
84 for (int i = 0; (clk = fdtbus_clock_get_index(phandle, i)); i++)
85 if (clk_enable(clk) != 0) {
|
| plmmc_fdt.c | 69 struct clk *clk; local in function:plmmc_fdt_attach
79 clk = fdtbus_clock_get_index(phandle, 0);
80 if (clk == NULL) {
85 if (clk_enable(clk) != 0) {
97 sc->sc_clock_freq = clk_get_rate(clk);
|
| /src/sys/arch/arm/samsung/ |
| exynos_ehci.c | 75 struct clk *clk; local in function:exynos_ehci_attach
88 clk = fdtbus_clock_get(phandle, "usbhost");
89 if (clk == NULL || clk_enable(clk) != 0) {
|
| exynos_ohci.c | 75 struct clk *clk; local in function:exynos_ohci_attach
88 clk = fdtbus_clock_get(phandle, "usbhost");
89 if (clk == NULL || clk_enable(clk) != 0) {
|
| /src/sys/arch/arm/sunxi/ |
| sun9i_a80_mmcclk.c | 48 { .compat = "allwinner,sun9i-a80-mmc-config-clk" },
84 struct clk *clk; local in function:sun9i_a80_mmcclk_attach
96 clk = fdtbus_clock_get(phandle, "ahb");
97 if (clk == NULL || clk_enable(clk) != 0) {
|
| sunxi_sata.c | 78 struct clk *clk; local in function:sunxi_sata_attach
106 for (i = 0; (clk = fdtbus_clock_get_index(phandle, i)) != NULL; i++)
107 if (clk_enable(clk) != 0) {
|
| /src/sys/arch/arm/ti/ |
| ti_ehci.c | 78 struct clk *clk; local in function:ti_ehci_attach
92 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)
93 if (clk_enable(clk) != 0) {
|
| /src/sys/arch/vax/vax/ |
| ka410.c | 154 volatile struct ka410_clock *clk = (volatile void *)clk_page; local in function:ka410_clrf
160 clk->cpmbx = (clk->cpmbx & ~0x30);
|
| /src/sys/dev/mvme/ |
| osiop_pcctwo.c | 108 int clk, ctest7; local in function:osiop_pcctwo_attach
121 clk = cpuspeed;
124 clk = cpuspeed * 2;
137 sc->sc_osiop.sc_clock_freq = clk;
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| imx8qm.dtsi | 157 clk: clock-controller { label
158 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
|
| imx8qxp.dtsi | 62 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
73 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
84 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
95 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
167 clk: clock-controller { label
168 compatible = "fsl,imx8qxp-clk";
|
| /src/sys/arch/mips/mips/ |
| mips_mcclock.c | 85 volatile struct mcclock_pad32_clockdatum *clk = (void *)mcclock_addr; local in function:mips_mc_cpuspeed
97 saved_rega = clk[MC_REGA].datum;
98 saved_regb = clk[MC_REGB].datum;
104 clk[MC_REGA].datum = MC_BASE_32_KHz | MC_RATE_256_Hz;
105 clk[MC_REGB].datum = MC_REGB_BINARY|MC_REGB_24HR|MC_REGB_PIE| MC_REGB_SQWE;
111 clk[MC_REGA].datum = saved_rega;
112 clk[MC_REGB].datum = saved_regb;
145 volatile struct mcclock_pad32_clockdatum *clk = mcclock_addr; local in function:mips_mcclock_tickloop
148 junk = clk[MC_REGC].datum;
156 junk = clk[MC_REGC].datum
[all...] |
| /src/sys/arch/sparc64/dev/ |
| pcfiic_ebus.c | 114 int clk = prom_getpropint(findroot(), "clock-frequency", 0); local in function:pcfiic_ebus_attach
116 if (clk < 105000000)
118 else if (clk < 160000000)
|
| /src/sys/dev/clk/ |
| clk_backend.h | 34 #include <dev/clk/clk.h>
43 struct clk { struct
51 struct clk *(*get)(void *, const char *);
52 void (*put)(void *, struct clk *);
54 u_int (*get_rate)(void *, struct clk *);
55 int (*set_rate)(void *, struct clk *, u_int);
56 u_int (*round_rate)(void *, struct clk *, u_int);
57 int (*enable)(void *, struct clk *);
58 int (*disable)(void *, struct clk *);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvif/ |
| if0003.h | 33 __u32 clk; member in struct:nvif_perfdom_read_v0
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/bitmain/ |
| bm1880.dtsi | 104 clk: clock-controller@e8 { label in label:sctrl
105 compatible = "bitmain,bm1880-clk";
177 clocks = <&clk BM1880_CLK_UART_500M>,
178 <&clk BM1880_CLK_APB_UART>;
190 clocks = <&clk BM1880_CLK_UART_500M>,
191 <&clk BM1880_CLK_APB_UART>;
203 clocks = <&clk BM1880_CLK_UART_500M>,
204 <&clk BM1880_CLK_APB_UART>;
216 clocks = <&clk BM1880_CLK_UART_500M>,
217 <&clk BM1880_CLK_APB_UART>
[all...] |
