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    Searched defs:clks (Results 1 - 24 of 24) sorted by relevancy

  /src/sys/arch/arm/sunxi/
sunxi_de2_ccu.c 82 struct sunxi_ccu_clk *clks; member in struct:sunxi_de2_ccu_config
89 .clks = sun8i_h3_de2_ccu_clks,
96 .clks = sun8i_h3_de2_ccu_clks,
139 sc->sc_clks = conf->clks;
  /src/sys/arch/arm/rockchip/
rk_v1crypto.c 103 const char *const clks[]; member in struct:rk_v1crypto_data
108 .clks = {"aclk", "hclk", "sclk", "apb_pclk"},
113 .clks = {"hclk_master", "hclk_slave", "sclk"},
144 const char *const *clks = config->clks; local
164 if (fdtbus_clock_enable(phandle, clks[i], true) != 0) {
165 aprint_error(": couldn't enable %s clock\n", clks[i]);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
amdgpu_display_mode_vba.c 379 display_clocks_and_cfg_st *clks = &pipes[j].clks_cfg; local
519 mode_lib->vba.DPPCLK[mode_lib->vba.NumberOfActivePlanes] = clks->dppclk_mhz;
  /src/sys/external/isc/atheros_hal/dist/ar5210/
ar5210_misc.c 440 u_int clks = OS_REG_READ(ah, AR_IFS0) & 0x7ff; local
441 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
465 u_int clks = OS_REG_READ(ah, AR_SLOT_TIME) & 0xffff; local
466 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
491 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); local
492 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
538 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); local
539 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
  /src/sys/arch/arm/ti/
am18xx_psc.c 62 struct am18xx_psc_clk *clks; member in struct:am18xx_psc_config
160 .clks = am18xx_psc0_clks,
165 .clks = am18xx_psc1_clks,
346 sc->sc_clks = config->clks;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
amdgpu_renoir_ppt.c 267 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
420 enum smu_clk_type clks[] = { local
426 for (i = 0; i < ARRAY_SIZE(clks); i++) {
427 clk_type = clks[i];
amdgpu_navi10_ppt.c 1101 enum smu_clk_type clks[] = { local
1107 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1108 clk_type = clks[i];
1128 enum smu_clk_type clks[] = { local
1134 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1135 clk_type = clks[i];
  /src/sys/external/isc/atheros_hal/dist/ar5211/
ar5211_misc.c 443 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff; local
444 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
468 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff; local
469 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
494 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); local
495 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
541 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); local
542 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
clk_mgr.h 192 struct dc_clocks clks; member in struct:clk_mgr
  /src/sys/external/isc/atheros_hal/dist/
ah.c 356 u_int clks; local
360 clks = usecs * CLOCK_RATE[ath_hal_chan2wmode(ah, c)];
362 clks <<= 1;
364 clks >>= 1;
366 clks >>= 2;
368 clks = usecs * CLOCK_RATE[WIRELESS_MODE_11b];
369 return clks;
373 ath_hal_mac_usec(struct ath_hal *ah, u_int clks)
380 usec = clks / CLOCK_RATE[ath_hal_chan2wmode(ah, c)];
388 usec = clks / CLOCK_RATE[WIRELESS_MODE_11b]
    [all...]
  /src/sys/external/isc/atheros_hal/dist/ar5212/
ar5212_misc.c 464 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff; local
465 return ath_hal_mac_usec(ah, clks)+2; /* convert from system clocks */
489 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff; local
490 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
515 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); local
516 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
562 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); local
563 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_resource.c 1040 struct dm_pp_clock_levels clks = {0}; local
1058 &clks);
1061 clks.clocks_in_khz[clks.num_levels-1], 1000);
1063 clks.clocks_in_khz[clks.num_levels/8], 1000);
1065 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1067 clks.clocks_in_khz[clks.num_levels*3/8], 1000)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu8_hwmgr.c 762 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; local
763 if (clks == 0)
764 clks = SMU8_MIN_DEEP_SLEEP_SCLK;
766 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
770 clks);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_resource.c 1259 struct dm_pp_clock_levels clks = {0}; local
1265 &clks);
1268 clks.clocks_in_khz[clks.num_levels-1], 1000);
1270 clks.clocks_in_khz[clks.num_levels/8], 1000);
1272 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1274 clks.clocks_in_khz[clks.num_levels*3/8], 1000)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
amdgpu_display_rq_dlg_calc_20.c 785 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; local
800 double dppclk_freq_in_mhz = clks->dppclk_mhz;
801 double dispclk_freq_in_mhz = clks->dispclk_mhz;
802 double refclk_freq_in_mhz = clks->refclk_mhz;
amdgpu_display_rq_dlg_calc_20v2.c 785 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; local
800 double dppclk_freq_in_mhz = clks->dppclk_mhz;
801 double dispclk_freq_in_mhz = clks->dispclk_mhz;
802 double refclk_freq_in_mhz = clks->refclk_mhz;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
amdgpu_display_rq_dlg_calc_21.c 831 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; local
846 double dppclk_freq_in_mhz = clks->dppclk_mhz;
847 double dispclk_freq_in_mhz = clks->dispclk_mhz;
848 double refclk_freq_in_mhz = clks->refclk_mhz;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_ci_smumgr.c 356 CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
1090 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; local
1096 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
amdgpu_iceland_smumgr.c 853 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
854 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
857 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
860 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
1112 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1135 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1137 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; local
1146 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
    [all...]
amdgpu_tonga_smumgr.c 596 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
597 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
600 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
603 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
864 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
887 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
889 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; local
898 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
    [all...]
  /src/sys/arch/arm/amlogic/
mesong12_clkc.c 177 struct meson_clk_clk *clks; member in struct:mesong12_clkc_config
1482 .clks = mesong12a_clkc_clks,
1488 .clks = mesong12b_clkc_clks,
1526 sc->sc_clks = conf->clks;
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ci_dpm.c 2848 u32 clks = reference_clock * 5 / ss.rate; local
2855 mpll_ss2 |= CLKS(clks);
radeon_si_dpm.c 4932 u32 clks = reference_clock * 5 / ss.rate; local
4939 mpll_ss2 |= CLKS(clks);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si_dpm.c 5396 u32 clks = reference_clock * 5 / ss.rate; local
5403 mpll_ss2 |= CLKS(clks);

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