| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_hw_sequencer.c | 84 enum bp_pipe_control_action cntl; local in function:dce100_enable_display_power_gating
88 cntl = ASIC_PIPE_INIT;
90 cntl = ASIC_PIPE_ENABLE;
92 cntl = ASIC_PIPE_DISABLE;
97 dcb, controller_id + 1, cntl);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_hw_sequencer.c | 125 enum bp_pipe_control_action cntl; local in function:dce112_enable_display_power_gating
132 cntl = ASIC_PIPE_INIT;
134 cntl = ASIC_PIPE_ENABLE;
136 cntl = ASIC_PIPE_DISABLE;
141 dcb, controller_id + 1, cntl);
|
| /src/sys/arch/arm/amlogic/ |
| meson8b_clkc.c | 123 uint32_t cntl = CLK_READ(sc, HHI_SYS_PLL_CNTL); local in function:meson8b_clkc_pll_sys_set_rate
150 cntl &= ~HHI_SYS_PLL_CNTL_MUL;
151 cntl |= __SHIFTIN(new_mul, HHI_SYS_PLL_CNTL_MUL);
152 cntl &= ~HHI_SYS_PLL_CNTL_DIV;
153 cntl |= __SHIFTIN(new_div, HHI_SYS_PLL_CNTL_DIV);
154 cntl &= ~HHI_SYS_PLL_CNTL_OD;
155 cntl |= __SHIFTIN(new_od, HHI_SYS_PLL_CNTL_OD);
165 CLK_WRITE(sc, HHI_SYS_PLL_CNTL, cntl);
|
| meson_sdhc.c | 597 uint32_t cntl; local in function:meson_sdhc_bus_width
599 cntl = SDHC_READ(sc, SD_CNTL_REG);
600 cntl &= ~SD_CNTL_DAT_TYPE;
603 cntl |= __SHIFTIN(0, SD_CNTL_DAT_TYPE);
606 cntl |= __SHIFTIN(1, SD_CNTL_DAT_TYPE);
609 cntl |= __SHIFTIN(2, SD_CNTL_DAT_TYPE);
615 SDHC_WRITE(sc, SD_CNTL_REG, cntl);
630 uint32_t cmdval = 0, cntl, srst, pdma, ictl; local in function:meson_sdhc_exec_command
664 cntl = SDHC_READ(sc, SD_CNTL_REG);
665 cntl &= ~SD_CNTL_PACK_LEN
[all...] |
| /src/sys/arch/hppa/gsc/ |
| harmony.c | 214 uint32_t cntl; local in function:harmony_attach
231 cntl = READ_REG(sc, HARMONY_ID);
232 switch ((cntl & ID_REV_MASK)) {
239 (cntl & ID_REV_MASK) >> ID_REV_SHIFT);
313 cntl = READ_REG(sc, HARMONY_CNTL);
314 rev = (cntl & CNTL_CODEC_REV_MASK) >> CNTL_CODEC_REV_SHIFT;
1181 /* XXX leave these bits alone or the chip will not come out of CNTL */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_dbgdev.c | 238 union TCP_WATCH_CNTL_BITS *cntl,
246 cntl->u32All = 0;
249 cntl->bitfields.mask =
253 cntl->bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
262 cntl->bitfields.mode = adw_info->watch_mode[index];
263 cntl->bitfields.vmid = (uint32_t) vmid;
265 cntl->u32All |= ADDRESS_WATCH_REG_CNTL_ATC_BIT;
267 pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask);
279 union TCP_WATCH_CNTL_BITS cntl; local in function:dbgdev_address_watch_nodiq
293 cntl.u32All = 0
346 union TCP_WATCH_CNTL_BITS cntl; local in function:dbgdev_address_watch_diq
[all...] |
| /src/libexec/rlogind/ |
| rlogind.c | 455 char cntl; local in function:protocol
492 cc = read(p, &cntl, 1);
493 if (cc == 1 && pkcontrol(cntl)) {
494 cntl |= oobdata[0];
495 send(f, &cntl, 1, MSG_OOB);
496 if (cntl & TIOCPKT_FLUSHWRITE)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_amdkfd_gfx_v7.c | 589 union TCP_WATCH_CNTL_BITS cntl; local in function:kgd_address_watch_disable
592 cntl.u32All = 0;
594 cntl.bitfields.valid = 0;
595 cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
596 cntl.bitfields.atc = 1;
601 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
613 union TCP_WATCH_CNTL_BITS cntl; local in function:kgd_address_watch_execute
615 cntl.u32All = cntl_val;
618 cntl.bitfields.valid = 0;
620 ADDRESS_WATCH_REG_CNTL], cntl.u32All)
[all...] |
| kv_dpm.h | 87 u32 cntl; member in struct:kv_lcac_config_reg
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_link_encoder.c | 131 struct bp_transmitter_control *cntl)
136 result = bp->funcs->transmitter_control(bp, cntl);
835 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_hw_init
838 cntl.action = TRANSMITTER_CONTROL_INIT;
839 cntl.engine_id = ENGINE_ID_UNKNOWN;
840 cntl.transmitter = enc110->base.transmitter;
841 cntl.connector_obj_id = enc110->base.connector;
842 cntl.lanes_number = LANE_COUNT_FOUR;
843 cntl.coherent = false;
844 cntl.hpd_sel = enc110->base.hpd_source
928 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_enable_tmds_output
964 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_enable_lvds_output
996 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_enable_dp_output
1035 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_enable_dp_mst_output
1075 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_disable_output
1120 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_link_encoder_dp_set_lane_settings
[all...] |
| amdgpu_dce_stream_encoder.c | 564 struct bp_encoder_control cntl = {0}; local in function:dce110_stream_encoder_hdmi_set_stream_attribute
566 cntl.action = ENCODER_CONTROL_SETUP;
567 cntl.engine_id = enc110->base.id;
568 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
569 cntl.enable_dp_audio = enable_audio;
570 cntl.pixel_clock = actual_pix_clk_khz;
571 cntl.lanes_number = LANE_COUNT_FOUR;
574 enc110->base.bp, &cntl) != BP_RESULT_OK)
677 struct bp_encoder_control cntl = {0}; local in function:dce110_stream_encoder_dvi_set_stream_attribute
679 cntl.action = ENCODER_CONTROL_SETUP
702 struct bp_encoder_control cntl = {0}; local in function:dce110_stream_encoder_lvds_set_stream_attribute
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_link_encoder.c | 103 struct bp_transmitter_control *cntl)
108 result = bp->funcs->transmitter_control(bp, cntl);
828 struct bp_transmitter_control cntl = { 0 }; local in function:dcn10_link_encoder_hw_init
831 cntl.action = TRANSMITTER_CONTROL_INIT;
832 cntl.engine_id = ENGINE_ID_UNKNOWN;
833 cntl.transmitter = enc10->base.transmitter;
834 cntl.connector_obj_id = enc10->base.connector;
835 cntl.lanes_number = LANE_COUNT_FOUR;
836 cntl.coherent = false;
837 cntl.hpd_sel = enc10->base.hpd_source
922 struct bp_transmitter_control cntl = { 0 }; local in function:dcn10_link_encoder_enable_tmds_output
958 struct bp_transmitter_control cntl = { 0 }; local in function:dcn10_link_encoder_enable_dp_output
997 struct bp_transmitter_control cntl = { 0 }; local in function:dcn10_link_encoder_enable_dp_mst_output
1037 struct bp_transmitter_control cntl = { 0 }; local in function:dcn10_link_encoder_disable_output
1086 struct bp_transmitter_control cntl = { 0 }; local in function:dcn10_link_encoder_dp_set_lane_settings
[all...] |
| amdgpu_dcn10_stream_encoder.c | 502 struct bp_encoder_control cntl = {0}; local in function:enc1_stream_encoder_hdmi_set_stream_attribute
504 cntl.action = ENCODER_CONTROL_SETUP;
505 cntl.engine_id = enc1->base.id;
506 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
507 cntl.enable_dp_audio = enable_audio;
508 cntl.pixel_clock = actual_pix_clk_khz;
509 cntl.lanes_number = LANE_COUNT_FOUR;
512 enc1->base.bp, &cntl) != BP_RESULT_OK)
608 struct bp_encoder_control cntl = {0}; local in function:enc1_stream_encoder_dvi_set_stream_attribute
610 cntl.action = ENCODER_CONTROL_SETUP
[all...] |
| /src/sys/arch/x86/pci/ |
| ichlpcib.c | 789 uint8_t cntl; local in function:speedstep_sysctl_helper
799 cntl = SS_READ(sc, PMC_PM_CTRL);
800 SS_WRITE(sc, PMC_PM_CTRL, cntl | PMC_PM_SS_CNTL_ARB_DIS);
802 SS_WRITE(sc, PMC_PM_CTRL, cntl);
|
| /src/sys/dev/ic/ |
| dwc_gmac.c | 1529 uint32_t cntl = le32toh(desc->ddesc_cntl1); local in function:dwc_gmac_desc_std_set_len
1531 desc->ddesc_cntl1 = htole32((cntl & ~DDESC_CNTL_SIZE1MASK) |
1553 uint32_t cntl = le32toh(desc->ddesc_cntl1); local in function:dwc_gmac_desc_std_tx_set_first_frag
1555 desc->ddesc_cntl1 = htole32(cntl | DDESC_CNTL_TXFIRST);
1561 uint32_t cntl = le32toh(desc->ddesc_cntl1); local in function:dwc_gmac_desc_std_tx_set_last_frag
1563 desc->ddesc_cntl1 = htole32(cntl |
1682 aprint_normal("#%3zu (%08lx): status: %08x cntl: %08x "
1731 aprint_normal("#%3zu (%08lx): status: %08x cntl: %08x "
|
| adwlib.h | 721 u_int8_t cntl; /* Ucode flags and state (ADW_MC_QC_*). */ member in struct:adw_scsi_req_q
|
| advlib.h | 441 u_int8_t cntl; /* see below cntl values */ member in struct:asc_scisq_1
461 /* cntl values */
551 u_int8_t cntl; member in struct:asc_q_done_info
633 u_int8_t cntl; /* see below cntl values */ member in struct:asc_sg_list_q
639 /* cntl values */
1005 u_int16_t cntl; member in struct:asceep_config
|
| /src/sys/arch/mips/adm5120/dev/ |
| if_admswreg.h | 254 volatile uint32_t cntl; member in struct:admsw_desc
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| kv_dpm.h | 61 u32 cntl; member in struct:kv_lcac_config_reg
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_hw_sequencer.c | 206 enum bp_pipe_control_action cntl; local in function:dce110_enable_display_power_gating
214 cntl = ASIC_PIPE_INIT;
216 cntl = ASIC_PIPE_ENABLE;
218 cntl = ASIC_PIPE_DISABLE;
226 dcb, controller_id + 1, cntl);
727 struct bp_transmitter_control *cntl)
731 result = bios->funcs->transmitter_control(bios, cntl);
814 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_edp_power_control
858 cntl.action = power_up ?
861 cntl.transmitter = link->link_enc->transmitter
896 struct bp_transmitter_control cntl = { 0 }; local in function:dce110_edp_backlight_control
[all...] |
| /src/sys/dev/ieee1394/ |
| fwohci.c | 2305 uint32_t cntl, stat, cmd, match; local in function:dump_dma
2319 cntl = stat = OREAD(sc, dbch->off);
2324 "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2326 cntl,
|
| fwohcireg.h | 193 fwohcireg_t cntl; member in struct:ohci_dma
220 fwohcireg_t cntl; member in struct:ohci_itdma
293 fwohcireg_t phy_access; /* PHY cntl 0xec */
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_display_types.h | 1120 u32 base, cntl, size; member in struct:intel_plane::__anonde7c4d451608
|
| intel_display.c | 11238 u32 cntl = 0; local in function:i845_cursor_ctl_crtc
11241 cntl |= CURSOR_GAMMA_ENABLE;
11243 return cntl;
11312 u32 cntl = 0, base = 0, pos = 0, size = 0; local in function:i845_update_cursor
11319 cntl = plane_state->ctl |
11335 plane->cursor.cntl != cntl) {
11340 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
11344 plane->cursor.cntl = cntl;
11392 u32 cntl = 0; local in function:i9xx_cursor_ctl_crtc
11414 u32 cntl = 0; local in function:i9xx_cursor_ctl
11541 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; local in function:i9xx_update_cursor
[all...] |
