1 /* $NetBSD: if_admswreg.h,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2001 Wasabi Systems, Inc. 35 * All rights reserved. 36 * 37 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed for the NetBSD Project by 50 * Wasabi Systems, Inc. 51 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 52 * or promote products derived from this software without specific prior 53 * written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 #ifndef _IF_ADMSWREG_H_ 68 #define _IF_ADMSWREG_H_ 69 70 /* ADMSW_ definitions Copyright (c) 2007 David Young. */ 71 #define ADMSW_BOOT_DONE 0x0008 72 #define ADMSW_BOOT_DONE_BO __BIT(0) 73 #define ADMSW_SW_RES 0x000c 74 #define ADMSW_SW_RES_SWR __BITS(31, 0) 75 #define ADMSW_INT_ST 0x00b0 76 #define ADMSW_INT_MASK 0x00b4 77 78 #define ADMSW_INTR_RSVD __BITS(31, 25) 79 #define ADMSW_INTR_CPUH __BIT(24) 80 #define ADMSW_INTR_SDE __BIT(23) 81 #define ADMSW_INTR_RDE __BIT(22) 82 #define ADMSW_INTR_W1TE __BIT(21) 83 #define ADMSW_INTR_W0TE __BIT(20) 84 #define ADMSW_INTR_MI __BIT(19) 85 #define ADMSW_INTR_PSC __BIT(18) 86 #define ADMSW_INTR_BCS __BIT(16) 87 #define ADMSW_INTR_MD __BIT(15) 88 #define ADMSW_INTR_GQF __BIT(14) 89 #define ADMSW_INTR_CPQ __BIT(13) 90 #define ADMSW_INTR_P5QF __BIT(11) 91 #define ADMSW_INTR_P4QF __BIT(10) 92 #define ADMSW_INTR_P3QF __BIT(9) 93 #define ADMSW_INTR_P2QF __BIT(8) 94 #define ADMSW_INTR_P1QF __BIT(7) 95 #define ADMSW_INTR_P0QF __BIT(6) 96 #define ADMSW_INTR_LDF __BIT(5) 97 #define ADMSW_INTR_HDF __BIT(4) 98 #define ADMSW_INTR_RLD __BIT(3) 99 #define ADMSW_INTR_RHD __BIT(2) 100 #define ADMSW_INTR_SLD __BIT(1) 101 #define ADMSW_INTR_SHD __BIT(0) 102 103 #define ADMSW_INT_FMT \ 104 "\x10"\ 105 "\x01SHD"\ 106 "\x02SLD"\ 107 "\x03RHD"\ 108 "\x04RLD"\ 109 "\x05HDF"\ 110 "\x06LDF"\ 111 "\x07P0QF"\ 112 "\x08P1QF"\ 113 "\x09P2QF"\ 114 "\x0aP3QF"\ 115 "\x0bP4QF"\ 116 "\x0cP5QF"\ 117 "\x0e"\ 118 "CPQ"\ 119 "\x0fGQF"\ 120 "\x10MD"\ 121 "\x11"\ 122 "BCS"\ 123 "\x13PSC"\ 124 "\x14MI"\ 125 "\x15W0TE"\ 126 "\x16W1TE"\ 127 "\x17RDE"\ 128 "\x18SDE"\ 129 "\x19"\ 130 "CPUH" 131 132 #define CODE_REG 0x0000 133 #define SFTREST_REG 0x0004 134 #define BOOT_DONE_REG 0x0008 135 #define GLOBAL_ST_REG 0x0010 136 #define PHY_ST_REG 0x0014 137 #define PHY_ST_LINKUP (1 << 0) 138 #define PHY_ST_100M (1 << 8) 139 #define PHY_ST_FDX (1 << 16) 140 #define PORT_ST_REG 0x0018 141 #define MEM_CONTROL_REG 0x001C 142 #define SW_CONF_REG 0x0020 143 144 #define CPUP_CONF_REG 0x0024 145 #define CPUP_CONF_DCPUP 0x00000001 146 #define CPUP_CONF_CRCP 0x00000002 147 #define CPUP_CONF_BTM 0x00000004 148 #define CPUP_CONF_DUNP_SHIFT 9 149 #define CPUP_CONF_DUNP_MASK (0x3F << CPUP_CONF_DUNP_SHIFT) 150 #define CPUP_CONF_DMCP_SHIFT 16 151 #define CPUP_CONF_DMCP_MASK (0x3F << CPUP_CONF_DMCP_SHIFT) 152 #define CPUP_CONF_DBCP_SHIFT 24 153 #define CPUP_CONF_DBCP_MASK (0x3F << CPUP_CONF_DBCP_SHIFT) 154 155 #define PORT_CONF0_REG 0x0028 156 #define PORT_CONF0_DP_MASK 0x0000003F 157 #define PORT_CONF0_EMCP_MASK 0x00003F00 158 #define PORT_CONF0_EMCP_SHIFT 8 159 #define PORT_CONF0_EMBP_MASK 0x003F0000 160 #define PORT_CONF0_EMBP_SHIFT 16 161 #define PORT_CONF1_REG 0x002C 162 #define PORT_CONF2_REG 0x0030 163 164 #define VLAN_G1_REG 0x0040 165 #define VLAN_G2_REG 0x0044 166 #define SEND_TRIG_REG 0x0048 167 #define SRCH_CMD_REG 0x004C 168 #define ADDR_ST0_REG 0x0050 169 #define ADDR_ST1_REG 0x0054 170 #define MAC_WT0_REG 0x0058 171 #define MAC_WT0_WRITE 0x00000001 172 #define MAC_WT0_WRITE_DONE 0x00000002 173 #define MAC_WT0_FILTER_EN 0x00000004 174 #define MAC_WT0_VLANID_SHIFT 3 175 #define MAC_WT0_VLANID_MASK 0x00000038 176 #define MAC_WT0_VLANID_EN 0x00000040 177 #define MAC_WT0_PORTMAP_MASK 0x00001F80 178 #define MAC_WT0_PORTMAP_SHIFT 7 179 #define MAC_WT0_AGE_MASK (0x7 << 13) 180 #define MAC_WT0_AGE_STATIC (0x7 << 13) 181 #define MAC_WT0_AGE_VALID (0x1 << 13) 182 #define MAC_WT0_AGE_EMPTY 0 183 #define MAC_WT1_REG 0x005C 184 #define BW_CNTL0_REG 0x0060 185 #define BW_CNTL1_REG 0x0064 186 #define PHY_CNTL0_REG 0x0068 187 #define PHY_CNTL1_REG 0x006C 188 #define FC_TH_REG 0x0070 189 #define FC_TH_FCS_MASK 0x01FF0000 190 #define FC_TH_D2R_MASK 0x0000FF00 191 #define FC_TH_D2S_MASK 0x000000FF 192 #define ADJ_PORT_TH_REG 0x0074 193 #define PORT_TH_REG 0x0078 194 #define PHY_CNTL2_REG 0x007C 195 #define PHY_CNTL2_AUTONEG (1 << 0) 196 #define PHY_CNTL2_ANE_MASK 0x0000001F 197 #define PHY_CNTL2_SC_MASK 0x000003E0 198 #define PHY_CNTL2_SC_SHIFT 5 199 #define PHY_CNTL2_100M (1 << PHY_CNTL2_SC_SHIFT) 200 #define PHY_CNTL2_DC_MASK 0x00007C00 201 #define PHY_CNTL2_DC_SHIFT 10 202 #define PHY_CNTL2_FDX (1 << PHY_CNTL2_DC_SHIFT) 203 #define PHY_CNTL2_RFCV_MASK 0x000F8000 204 #define PHY_CNTL2_RFCV_SHIFT 15 205 #define PHY_CNTL2_PHYR_MASK 0x01F00000 206 #define PHY_CNTL2_PHYR_SHIFT 20 207 #define PHY_CNTL2_AMDIX_MASK 0x3E000000 208 #define PHY_CNTL2_AMDIX_SHIFT 25 209 #define PHY_CNTL2_RMAE 0x40000000 210 #define PHY_CNTL3_REG 0x0080 211 #define PHY_CNTL3_RNT 0x00000400 212 213 #define PRI_CNTL_REG 0x0084 214 #define VLAN_PRI_REG 0x0088 215 #define TOS_EN_REG 0x008C 216 #define TOS_MAP0_REG 0x0090 217 #define TOS_MAP1_REG 0x0094 218 #define CUSTOM_PRI1_REG 0x0098 219 #define CUSTOM_PRI2_REG 0x009C 220 221 #define EMPTY_CNT_REG 0x00A4 222 #define PORT_CNT_SEL_REG 0x00A8 223 #define PORT_CNT_REG 0x00AC 224 225 #define INT_MASK 0x1FDEFFF 226 227 #define GPIO_CONF0_REG 0x00B8 228 #define GPIO_CONF2_REG 0x00BC 229 230 #define SWAP_IN_REG 0x00C8 231 #define SWAP_OUT_REG 0x00CC 232 233 #define SEND_HBADDR_REG 0x00D0 234 #define SEND_LBADDR_REG 0x00D4 235 #define RECV_HBADDR_REG 0x00D8 236 #define RECV_LBADDR_REG 0x00DC 237 #define SEND_HWADDR_REG 0x00E0 238 #define SEND_LWADDR_REG 0x00E4 239 #define RECV_HWADDR_REG 0x00E8 240 #define RECV_LWADDR_REG 0x00EC 241 242 #define TIMER_INT_REG 0x00F0 243 #define TIMER_REG 0x00F4 244 245 #define PORT0_LED_REG 0x0100 246 #define PORT1_LED_REG 0x0104 247 #define PORT2_LED_REG 0x0108 248 #define PORT3_LED_REG 0x010c 249 #define PORT4_LED_REG 0x0110 250 251 /* Hardware descriptor format */ 252 struct admsw_desc { 253 volatile uint32_t data; 254 volatile uint32_t cntl; 255 volatile uint32_t len; 256 volatile uint32_t status; 257 } __attribute__((__packed__, __aligned__(4))); 258 259 #define ADM5120_DMA_MASK 0x01ffffff 260 #define ADM5120_DMA_OWN 0x80000000 /* buffer owner */ 261 #define ADM5120_DMA_RINGEND 0x10000000 /* Last in DMA ring */ 262 #define ADM5120_DMA_BUF2ENABLE 0x80000000 263 264 #define ADM5120_DMA_PORTID 0x00007000 265 #define ADM5120_DMA_PORTSHIFT 12 266 #define ADM5120_DMA_LEN 0x07ff0000 267 #define ADM5120_DMA_LENSHIFT 16 268 #define ADM5120_DMA_TYPE 0x00000003 269 #define ADM5120_DMA_TYPE_IP 0x00000000 270 #define ADM5120_DMA_TYPE_PPPOE 0x00000001 271 #define ADM5120_DMA_CSUM 0x80000000 272 #define ADM5120_DMA_CSUMFAIL 0x00000008 273 274 #define SW_DEVS 6 275 276 #if 0 277 /* CODE_REG */ 278 #define CODE_ID_MASK 0x00FFFF 279 #define CODE_ADM5120_ID 0x5120 280 281 #define CODE_REV_MASK 0x0F0000 282 #define CODE_REV_SHIFT 16 283 #define CODE_REV_ADM5120_0 0x8 284 285 #define CODE_CLK_MASK 0x300000 286 #define CODE_CLK_SHIFT 20 287 288 #define CPU_CLK_175MHZ 0x0 289 #define CPU_CLK_200MHZ 0x1 290 #define CPU_CLK_225MHZ 0x2 291 #define CPU_CLK_250MHZ 0x3 292 293 #define CPU_SPEED_175M (175000000/2) 294 #define CPU_SPEED_200M (200000000/2) 295 #define CPU_SPEED_225M (225000000/2) 296 #define CPU_SPEED_250M (250000000/2) 297 298 #define CPU_NAND_BOOT 0x01000000 299 #define CPU_DCACHE_2K_WAY (0x1 << 25) 300 #define CPU_DCACHE_2WAY (0x1 << 26) 301 #define CPU_ICACHE_2K_WAY (0x1 << 27) 302 #define CPU_ICACHE_2WAY (0x1 << 28) 303 304 #define CPU_GMII_SUPPORT 0x20000000 305 306 #define CPU_PQFP_MODE (0x1 << 29) 307 308 #define CPU_CACHE_LINE_SIZE 16 309 310 /* SftRest_REG */ 311 #define SOFTWARE_RESET 0x1 312 313 /* Boot_done_REG */ 314 #define BOOT_DONE 0x1 315 316 /* SWReset_REG */ 317 #define SWITCH_RESET 0x1 318 319 /* Global_St_REG */ 320 #define DATA_BUF_BIST_FAILED (0x1 << 0) 321 #define LINK_TAB_BIST_FAILED (0x1 << 1) 322 #define MC_TAB_BIST_FAILED (0x1 << 2) 323 #define ADDR_TAB_BIST_FAILED (0x1 << 3) 324 #define DCACHE_D_FAILED (0x3 << 4) 325 #define DCACHE_T_FAILED (0x1 << 6) 326 #define ICACHE_D_FAILED (0x3 << 7) 327 #define ICACHE_T_FAILED (0x1 << 9) 328 #define BIST_FAILED_MASK 0x03FF 329 330 #define ALLMEM_TEST_DONE (0x1 << 10) 331 332 #define SKIP_BLK_CNT_MASK 0x1FF000 333 #define SKIP_BLK_CNT_SHIFT 12 334 335 336 /* PHY_st_REG */ 337 #define PORT_LINK_MASK 0x0000001F 338 #define PORT_MII_LINKFAIL 0x00000020 339 #define PORT_SPEED_MASK 0x00001F00 340 341 #define PORT_GMII_SPD_MASK 0x00006000 342 #define PORT_GMII_SPD_10M 0 343 #define PORT_GMII_SPD_100M 0x00002000 344 #define PORT_GMII_SPD_1000M 0x00004000 345 346 #define PORT_DUPLEX_MASK 0x003F0000 347 #define PORT_FLOWCTRL_MASK 0x1F000000 348 349 #define PORT_GMII_FLOWCTRL_MASK 0x60000000 350 #define PORT_GMII_FC_ON 0x20000000 351 #define PORT_GMII_RXFC_ON 0x20000000 352 #define PORT_GMII_TXFC_ON 0x40000000 353 354 /* Port_st_REG */ 355 #define PORT_SECURE_ST_MASK 0x001F 356 #define MII_PORT_TXC_ERR 0x0080 357 358 /* Mem_control_REG */ 359 #define SDRAM_SIZE_4MBYTES 0x0001 360 #define SDRAM_SIZE_8MBYTES 0x0002 361 #define SDRAM_SIZE_16MBYTES 0x0003 362 #define SDRAM_SIZE_64MBYTES 0x0004 363 #define SDRAM_SIZE_128MBYTES 0x0005 364 #define SDRAM_SIZE_MASK 0x0007 365 366 #define MEMCNTL_SDRAM1_EN (0x1 << 5) 367 368 #define ROM_SIZE_DISABLE 0x0000 369 #define ROM_SIZE_512KBYTES 0x0001 370 #define ROM_SIZE_1MBYTES 0x0002 371 #define ROM_SIZE_2MBYTES 0x0003 372 #define ROM_SIZE_4MBYTES 0x0004 373 #define ROM_SIZE_8MBYTES 0x0005 374 #define ROM_SIZE_MASK 0x0007 375 376 #define ROM0_SIZE_SHIFT 8 377 #define ROM1_SIZE_SHIFT 16 378 379 380 /* SW_conf_REG */ 381 #define SW_AGE_TIMER_MASK 0x000000F0 382 #define SW_AGE_TIMER_DISABLE 0x0 383 #define SW_AGE_TIMER_FAST 0x00000080 384 #define SW_AGE_TIMER_300SEC 0x00000010 385 #define SW_AGE_TIMER_600SEC 0x00000020 386 #define SW_AGE_TIMER_1200SEC 0x00000030 387 #define SW_AGE_TIMER_2400SEC 0x00000040 388 #define SW_AGE_TIMER_4800SEC 0x00000050 389 #define SW_AGE_TIMER_9600SEC 0x00000060 390 #define SW_AGE_TIMER_19200SEC 0x00000070 391 //#define SW_AGE_TIMER_38400SEC 0x00000070 392 393 #define SW_BC_PREV_MASK 0x00000300 394 #define SW_BC_PREV_DISABLE 0 395 #define SW_BC_PREV_64BC 0x00000100 396 #define SW_BC_PREV_48BC 0x00000200 397 #define SW_BC_PREV_32BC 0x00000300 398 399 #define SW_MAX_LEN_MASK 0x00000C00 400 #define SW_MAX_LEN_1536 0 401 #define SW_MAX_LEN_1522 0x00000800 402 #define SW_MAX_LEN_1518 0x00000400 403 404 #define SW_DIS_COLABT 0x00001000 405 406 #define SW_HASH_ALG_MASK 0x00006000 407 #define SW_HASH_ALG_DIRECT 0 408 #define SW_HASH_ALG_XOR48 0x00002000 409 #define SW_HASH_ALG_XOR32 0x00004000 410 411 #define SW_DISABLE_BACKOFF_TIMER 0x00008000 412 413 #define SW_BP_NUM_MASK 0x000F0000 414 #define SW_BP_NUM_SHIFT 16 415 #define SW_BP_MODE_MASK 0x00300000 416 #define SW_BP_MODE_DISABLE 0 417 #define SW_BP_MODE_JAM 0x00100000 418 #define SW_BP_MODE_JAMALL 0x00200000 419 #define SW_BP_MODE_CARRIER 0x00300000 420 #define SW_RESRV_MC_FILTER 0x00400000 421 #define SW_BISR_DISABLE 0x00800000 422 423 #define SW_DIS_MII_WAS_TX 0x01000000 424 #define SW_BISS_EN 0x02000000 425 #define SW_BISS_TH_MASK 0x0C000000 426 #define SW_BISS_TH_SHIFT 26 427 #define SW_REQ_LATENCY_MASK 0xF0000000 428 #define SW_REQ_LATENCY_SHIFT 28 429 430 431 /* CPUp_conf_REG */ 432 #define SW_CPU_PORT_DISABLE 0x00000001 433 #define SW_PADING_CRC 0x00000002 434 #define SW_BRIDGE_MODE 0x00000004 435 436 #define SW_DIS_UN_SHIFT 9 437 #define SW_DIS_UN_MASK (0x3F << SW_DIS_UN_SHIFT) 438 #define SW_DIS_MC_SHIFT 16 439 #define SW_DIS_MC_MASK (0x3F << SW_DIS_MC_SHIFT) 440 #define SW_DIS_BC_SHIFT 24 441 #define SW_DIS_BC_MASK (0x3F << SW_DIS_BC_SHIFT) 442 443 444 /* Port_conf0_REG */ 445 #define SW_DISABLE_PORT_MASK 0x0000003F 446 #define SW_EN_MC_MASK 0x00003F00 447 #define SW_EN_MC_SHIFT 8 448 #define SW_EN_BP_MASK 0x003F0000 449 #define SW_EN_BP_SHIFT 16 450 #define SW_EN_FC_MASK 0x3F000000 451 #define SW_EN_FC_SHIFT 24 452 453 454 /* Port_conf1_REG */ 455 #define SW_DIS_SA_LEARN_MASK 0x0000003F 456 #define SW_PORT_BLOCKING_MASK 0x00000FC0 457 #define SW_PORT_BLOCKING_SHIFT 6 458 #define SW_PORT_BLOCKING_ON 0x1 459 460 #define SW_PORT_BLOCKING_MODE_MASK 0x0003F000 461 #define SW_PORT_BLOCKING_MODE_SHIFT 12 462 #define SW_PORT_BLOCKING_CTRLONLY 0x1 463 464 #define SW_EN_PORT_AGE_MASK 0x03F00000 465 #define SW_EN_PORT_AGE_SHIFT 20 466 #define SW_EN_SA_SECURED_MASK 0xFC000000 467 #define SW_EN_SA_SECURED_SHIFT 26 468 469 470 /* Port_conf2_REG */ 471 #define SW_GMII_AN_EN 0x00000001 472 #define SW_GMII_FORCE_SPD_MASK 0x00000006 473 #define SW_GMII_FORCE_SPD_10M 0 474 #define SW_GMII_FORCE_SPD_100M 0x2 475 #define SW_GMII_FORCE_SPD_1000M 0x4 476 477 #define SW_GMII_FORCE_FULL_DUPLEX 0x00000008 478 479 #define SW_GMII_FORCE_RXFC 0x00000010 480 #define SW_GMII_FORCE_TXFC 0x00000020 481 482 #define SW_GMII_EN 0x00000040 483 #define SW_GMII_REVERSE 0x00000080 484 485 #define SW_GMII_TXC_CHECK_EN 0x00000100 486 487 #define SW_LED_FLASH_TIME_MASK 0x00030000 488 #define SW_LED_FLASH_TIME_30MS 0 489 #define SW_LED_FLASH_TIME_60MS 0x00010000 490 #define SW_LED_FLASH_TIME_240MS 0x00020000 491 #define SW_LED_FLASH_TIME_480MS 0x00030000 492 493 494 /* Send_trig_REG */ 495 #define SEND_TRIG_LOW 0x0001 496 #define SEND_TRIG_HIGH 0x0002 497 498 499 /* Srch_cmd_REG */ 500 #define SW_MAC_SEARCH_START 0x000001 501 #define SW_MAX_SEARCH_AGAIN 0x000002 502 503 504 /* MAC_wt0_REG */ 505 #define SW_MAC_WRITE 0x00000001 506 #define SW_MAC_WRITE_DONE 0x00000002 507 #define SW_MAC_FILTER_EN 0x00000004 508 #define SW_MAC_VLANID_SHIFT 3 509 #define SW_MAC_VLANID_MASK 0x00000038 510 #define SW_MAC_VLANID_EN 0x00000040 511 #define SW_MAC_PORTMAP_MASK 0x00001F80 512 #define SW_MAC_PORTMAP_SHIFT 7 513 #define SW_MAC_AGE_MASK (0x7 << 13) 514 #define SW_MAC_AGE_STATIC (0x7 << 13) 515 #define SW_MAC_AGE_VALID (0x1 << 13) 516 #define SW_MAC_AGE_EMPTY 0 517 518 /* BW_cntl0_REG */ 519 #define SW_PORT_TX_NOLIMIT 0 520 #define SW_PORT_TX_64K 1 521 #define SW_PORT_TX_128K 2 522 #define SW_PORT_TX_256K 3 523 #define SW_PORT_TX_512K 4 524 #define SW_PORT_TX_1M 5 525 #define SW_PORT_TX_4M 6 526 #define SW_PORT_TX_10MK 7 527 528 /* BW_cntl1_REG */ 529 #define SW_TRAFFIC_SHAPE_IPG (0x1 << 31) 530 531 /* PHY_cntl0_REG */ 532 #define SW_PHY_ADDR_MASK 0x0000001F 533 #define PHY_ADDR_MAX 0x1f 534 #define SW_PHY_REG_ADDR_MASK 0x00001F00 535 #define SW_PHY_REG_ADDR_SHIFT 8 536 #define PHY_REG_ADDR_MAX 0x1f 537 #define SW_PHY_WRITE 0x00002000 538 #define SW_PHY_READ 0x00004000 539 #define SW_PHY_WDATA_MASK 0xFFFF0000 540 #define SW_PHY_WDATA_SHIFT 16 541 542 543 /* PHY_cntl1_REG */ 544 #define SW_PHY_WRITE_DONE 0x00000001 545 #define SW_PHY_READ_DONE 0x00000002 546 #define SW_PHY_RDATA_MASK 0xFFFF0000 547 #define SW_PHY_RDATA_SHIFT 16 548 549 /* FC_th_REG */ 550 /* Adj_port_th_REG */ 551 /* Port_th_REG */ 552 553 /* PHY_cntl2_REG */ 554 #define SW_PHY_AN_MASK 0x0000001F 555 #define SW_PHY_SPD_MASK 0x000003E0 556 #define SW_PHY_SPD_SHIFT 5 557 #define SW_PHY_DPX_MASK 0x00007C00 558 #define SW_PHY_DPX_SHIFT 10 559 #define SW_FORCE_FC_MASK 0x000F8000 560 #define SW_FORCE_FC_SHIFT 15 561 #define SW_PHY_NORMAL_MASK 0x01F00000 562 #define SW_PHY_NORMAL_SHIFT 20 563 #define SW_PHY_AUTOMDIX_MASK 0x3E000000 564 #define SW_PHY_AUTOMDIX_SHIFT 25 565 #define SW_PHY_REC_MCCAVERAGE 0x40000000 566 567 568 /* PHY_cntl3_REG */ 569 /* Pri_cntl_REG */ 570 /* VLAN_pri_REG */ 571 /* TOS_en_REG */ 572 /* TOS_map0_REG */ 573 /* TOS_map1_REG */ 574 /* Custom_pri1_REG */ 575 /* Custom_pri2_REG */ 576 /* Empty_cnt_REG */ 577 /* Port_cnt_sel_REG */ 578 /* Port_cnt_REG */ 579 580 581 /* SW_Int_st_REG & SW_Int_mask_REG */ 582 #define SEND_H_DONE_INT 0x0000001 583 #define SEND_L_DONE_INT 0x0000002 584 #define RX_H_DONE_INT 0x0000004 585 #define RX_L_DONE_INT 0x0000008 586 #define RX_H_DESC_FULL_INT 0x0000010 587 #define RX_L_DESC_FULL_INT 0x0000020 588 #define PORT0_QUE_FULL_INT 0x0000040 589 #define PORT1_QUE_FULL_INT 0x0000080 590 #define PORT2_QUE_FULL_INT 0x0000100 591 #define PORT3_QUE_FULL_INT 0x0000200 592 #define PORT4_QUE_FULL_INT 0x0000400 593 #define PORT5_QUE_FULL_INT 0x0000800 594 595 #define CPU_QUE_FULL_INT 0x0002000 596 #define GLOBAL_QUE_FULL_INT 0x0004000 597 #define MUST_DROP_INT 0x0008000 598 #define BC_STORM_INT 0x0010000 599 600 #define PORT_STATUS_CHANGE_INT 0x0040000 601 #define INTRUDER_INT 0x0080000 602 #define WATCHDOG0_EXPR_INT 0x0100000 603 #define WATCHDOG1_EXPR_INT 0x0200000 604 #define RX_DESC_ERR_INT 0x0400000 605 #define SEND_DESC_ERR_INT 0x0800000 606 #define CPU_HOLD_INT 0x1000000 607 #define SWITCH_INT_MASK 0x1FDEFFF 608 609 610 /* GPIO_conf0_REG */ 611 #define GPIO0_INPUT_MODE 0x00000001 612 #define GPIO1_INPUT_MODE 0x00000002 613 #define GPIO2_INPUT_MODE 0x00000004 614 #define GPIO3_INPUT_MODE 0x00000008 615 #define GPIO4_INPUT_MODE 0x00000010 616 #define GPIO5_INPUT_MODE 0x00000020 617 #define GPIO6_INPUT_MODE 0x00000040 618 #define GPIO7_INPUT_MODE 0x00000080 619 620 #define GPIO0_OUTPUT_MODE 0 621 #define GPIO1_OUTPUT_MODE 0 622 #define GPIO2_OUTPUT_MODE 0 623 #define GPIO3_OUTPUT_MODE 0 624 #define GPIO4_OUTPUT_MODE 0 625 #define GPIO5_OUTPUT_MODE 0 626 #define GPIO6_OUTPUT_MODE 0 627 #define GPIO7_OUTPUT_MODE 0 628 629 #define GPIO0_INPUT_MASK 0x00000100 630 #define GPIO1_INPUT_MASK 0x00000200 631 #define GPIO2_INPUT_MASK 0x00000400 632 #define GPIO3_INPUT_MASK 0x00000800 633 #define GPIO4_INPUT_MASK 0x00001000 634 #define GPIO5_INPUT_MASK 0x00002000 635 #define GPIO6_INPUT_MASK 0x00004000 636 #define GPIO7_INPUT_MASK 0x00008000 637 638 #define GPIO0_OUTPUT_EN 0x00010000 639 #define GPIO1_OUTPUT_EN 0x00020000 640 #define GPIO2_OUTPUT_EN 0x00040000 641 #define GPIO3_OUTPUT_EN 0x00080000 642 #define GPIO4_OUTPUT_EN 0x00100000 643 #define GPIO5_OUTPUT_EN 0x00200000 644 #define GPIO6_OUTPUT_EN 0x00400000 645 #define GPIO7_OUTPUT_EN 0x00800000 646 647 #define GPIO_CONF0_OUTEN_MASK 0x00ff0000 648 649 #define GPIO0_OUTPUT_HI 0x01000000 650 #define GPIO1_OUTPUT_HI 0x02000000 651 #define GPIO2_OUTPUT_HI 0x04000000 652 #define GPIO3_OUTPUT_HI 0x08000000 653 #define GPIO4_OUTPUT_HI 0x10000000 654 #define GPIO5_OUTPUT_HI 0x20000000 655 #define GPIO6_OUTPUT_HI 0x40000000 656 #define GPIO7_OUTPUT_HI 0x80000000 657 658 #define GPIO0_OUTPUT_LOW 0 659 #define GPIO1_OUTPUT_LOW 0 660 #define GPIO2_OUTPUT_LOW 0 661 #define GPIO3_OUTPUT_LOW 0 662 #define GPIO4_OUTPUT_LOW 0 663 #define GPIO5_OUTPUT_LOW 0 664 #define GPIO6_OUTPUT_LOW 0 665 #define GPIO7_OUTPUT_LOW 0 666 667 668 /* GPIO_conf2_REG */ 669 #define EXTIO_WAIT_EN (0x1 << 6) 670 #define EXTIO_CS1_INT1_EN (0x1 << 5) 671 #define EXTIO_CS0_INT0_EN (0x1 << 4) 672 673 /* Timer_int_REG */ 674 #define SW_TIMER_INT_DISABLE 0x10000 675 #define SW_TIMER_INT 0x1 676 677 /* Timer_REG */ 678 #define SW_TIMER_EN 0x10000 679 #define SW_TIMER_MASK 0xffff 680 #define SW_TIMER_10MS_TICKS 0x3D09 681 #define SW_TIMER_1MS_TICKS 0x61A 682 #define SW_TIMER_100US_TICKS 0x9D 683 684 685 /* Port0_LED_REG, Port1_LED_REG, Port2_LED_REG, Port3_LED_REG, Port4_LED_REG*/ 686 #define GPIOL_INPUT_MODE 0x00 687 #define GPIOL_OUTPUT_FLASH 0x01 688 #define GPIOL_OUTPUT_LOW 0x02 689 #define GPIOL_OUTPUT_HIGH 0x03 690 #define GPIOL_LINK_LED 0x04 691 #define GPIOL_SPEED_LED 0x05 692 #define GPIOL_DUPLEX_LED 0x06 693 #define GPIOL_ACT_LED 0x07 694 #define GPIOL_COL_LED 0x08 695 #define GPIOL_LINK_ACT_LED 0x09 696 #define GPIOL_DUPLEX_COL_LED 0x0A 697 #define GPIOL_10MLINK_ACT_LED 0x0B 698 #define GPIOL_100MLINK_ACT_LED 0x0C 699 #define GPIOL_CTRL_MASK 0x0F 700 701 #define GPIOL_INPUT_MASK 0x7000 702 #define GPIOL_INPUT_0_MASK 0x1000 703 #define GPIOL_INPUT_1_MASK 0x2000 704 #define GPIOL_INPUT_2_MASK 0x4000 705 706 #define PORT_LED0_SHIFT 0 707 #define PORT_LED1_SHIFT 4 708 #define PORT_LED2_SHIFT 8 709 #endif 710 #endif /* _IF_ADMSWREG_H_ */ 711
Indexes created Sat Sep 20 22:09:52 GMT 2025