| /src/sys/arch/epoc32/stand/e32boot/ldd/ |
| epoc32.h | 32 CPU *cpu; member in class:EPOC32
|
| /src/sys/arch/m68k/m68k/ |
| procfs_machdep.c | 21 const char *cpu, *mmu, *fpu; local in function:procfs_getcpuinfstr
26 cpu = "68020";
29 cpu = "68030";
32 cpu = "68040";
35 cpu = "68060";
38 cpu = "680x0";
83 "CPU:\t\t%s\n"
90 cpu, mmu, fpu);
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| am3517.dtsi | 24 cpu: cpu@0 { label
33 compatible = "operating-points-v2-ti-cpu";
|
| omap34xx.dtsi | 18 cpu: cpu@0 { label
28 compatible = "operating-points-v2-ti-cpu";
180 #include "omap3-cpu-thermal.dtsi"
|
| omap36xx.dtsi | 23 cpu: cpu@0 { label
33 compatible = "operating-points-v2-ti-cpu";
221 #include "omap3-cpu-thermal.dtsi"
|
| /src/sys/arch/hpc/stand/hpcboot/ |
| framebuffer.h | 35 uint32_t cpu, machine; member in struct:FrameBufferInfo::framebuffer_info
|
| hpcmenu.cpp | 373 uint32_t cpu = _pref.platid_hi; local in function:HpcMenuInterface::boot
377 for (; tab->cpu; tab++) {
378 if (tab->cpu == cpu && tab->machine == machine) {
|
| /src/sys/arch/hpc/stand/hpcboot/sh3/ |
| sh_console.h | 47 uint32_t cpu, machine; member in struct:SHConsole::console_info
|
| /src/sys/dev/acpi/ |
| acpi_srat.h | 46 * entries or ACPI CPU device have a _CDM.
61 struct acpisrat_cpu **cpu; /* Array of cpus */ member in struct:acpisrat_node
|
| /src/sys/external/bsd/common/linux/ |
| linux_srcu.c | 42 * sections, on each CPU we store two counts of numbers of
55 * no new readers -- srcu uses two counts per CPU instead of one
126 * Internal subroutine: Add delta to the local CPU's count of
134 struct srcu_cpu *cpu; local in function:srcu_adjust
137 cpu = percpu_getref(srcu->srcu_percpu);
138 cpu->src_count[epoch] += delta;
166 * No stronger, inter-CPU memory barrier is needed: if there is
189 * All side effects have completed on this CPU before we
192 * No stronger, inter-CPU memory barrier is needed: if there is
232 * readers on this CPU in the inactive epoch to the global coun
239 struct srcu_cpu *cpu; local in function:synchronize_srcu_xc
[all...] |
| /src/sys/arch/evbmips/sbmips/ |
| cpu.c | 1 /* $NetBSD: cpu.c,v 1.4 2023/12/05 19:16:48 andvar Exp $ */
36 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.4 2023/12/05 19:16:48 andvar Exp $");
41 #include <sys/cpu.h>
63 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc),
89 struct cpu_softc * const cpu = device_private(self); local in function:cpu_attach
96 /* XXX this code must run on the target CPU */
101 /* Determine CPU frequency */
103 /* XXX: We should determine the CPU frequency from a time source
104 * not coupled with the CPU crystal, like the RTC. Unfortunately
130 cpu->sb1cpu_dev = self
[all...] |
| /src/sys/arch/sbmips/sbmips/ |
| cpu.c | 1 /* $NetBSD: cpu.c,v 1.24 2023/12/05 19:19:26 andvar Exp $ */
36 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.24 2023/12/05 19:19:26 andvar Exp $");
41 #include <sys/cpu.h>
62 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc),
88 struct cpu_softc * const cpu = device_private(self); local in function:cpu_attach
95 /* XXX this code must run on the target CPU */
100 /* Determine CPU frequency */
102 /* XXX: We should determine the CPU frequency from a time source
103 * not coupled with the CPU crystal, like the RTC. Unfortunately
129 cpu->sb1cpu_dev = self
[all...] |
| /src/sys/arch/hppa/hppa/ |
| ipifuncs.c | 29 #include <machine/cpu.h>
107 struct iomod *cpu; local in function:hppa_ipi_send
113 * Send an IPI to the specified CPU by triggering EIR{1} (irq 30).
119 * the silicon or firmware on the target CPU that effectively
122 * if (atomic_load_acquire(&cpu->io_eir)) {
126 cpu = (struct iomod *)(ci->ci_hpa);
127 atomic_store_release(&cpu->io_eir, 1);
158 /* Turn off interrupts and halt CPU. */
174 /* Unicast: remote CPU. */
177 /* Broadcast: all, but local CPU (caller will handle it). *
[all...] |
| /src/sys/arch/hppa/dev/ |
| cpu.c | 1 /* $NetBSD: cpu.c,v 1.3 2022/02/14 08:12:48 riastradh Exp $ */
3 /* $OpenBSD: cpu.c,v 1.29 2009/02/08 18:33:28 miod Exp $ */
32 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2022/02/14 08:12:48 riastradh Exp $");
64 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc),
105 /* Print the CPU chip name, nickname, and rev. */
117 /* Print the CPU type, spec, level, category, and speed. */
198 aprint_error(": unable to allocate CPU stack!\n");
228 struct iomod *cpu; local in function:cpu_boot_secondary_processors
244 * Release the specified CPU by triggering an EIR{0}.
253 * if (atomic_load_acquire(&cpu->io_eir) == 0)
[all...] |
| /src/sys/arch/mvme68k/stand/netboot/ |
| config.h | 55 u_char cpu; member in struct:brdid
|
| /src/sys/arch/ofppc/stand/ofwboot/ |
| boot.c | 86 #include <machine/cpu.h>
192 int chosen, cpu, cpunode, j, is64=0; local in function:main
217 if (OF_getprop(chosen, "cpu", &cpu, sizeof cpu) == sizeof(cpu)) {
218 cpunode = OF_instance_to_package(cpu);
|
| /src/sys/arch/powerpc/booke/ |
| e500_timer.c | 45 #include <sys/cpu.h>
70 openpic_write(struct cpu_softc *cpu, bus_size_t offset, uint32_t val)
73 return bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh,
82 struct cpu_softc * const cpu = ci->ci_softc; local in function:e500_clock_intr
88 if (!cpu->cpu_ticks_per_clock_intr)
101 uint64_t latency = now - (ci->ci_lastintr + cpu->cpu_ticks_per_clock_intr);
105 if (now < ci->ci_lastintr + cpu->cpu_ticks_per_clock_intr)
108 nticks = 1 + latency / cpu->cpu_ticks_per_clock_intr;
109 latency %= cpu->cpu_ticks_per_clock_intr
151 struct cpu_softc * const cpu = ci->ci_softc; local in function:cpu_initclocks
[all...] |
| /src/sys/arch/ofppc/ofppc/ |
| cpu.c | 1 /* $NetBSD: cpu.c,v 1.17 2023/11/03 20:25:13 andvar Exp $ */
33 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.17 2023/11/03 20:25:13 andvar Exp $");
62 #include <machine/cpu.h>
80 CFATTACH_DECL_NEW(cpu, 0,
173 int node, cpu=-1; local in function:cpu_OFgetcache
186 cpu = node;
190 if (cpu == -1)
192 /* now we have cpu */
194 cpu_OFprintcacheinfo(cpu);
195 for (node = OF_child(cpu); node; node = OF_peer(node))
[all...] |
| /src/sys/arch/arm/nxp/ |
| imx7_gpc.c | 56 /* Mapping of CPU number to GPC_IMR1_COREx base offset */
177 for (u_int cpu = 0; cpu < (mpsafe ? ncpu : 1); cpu++) { local in function:imx7gpc_mask
179 GPC_IMRn_COREx(reg, cpu));
182 GPC_IMRn_COREx(reg, cpu), val);
193 for (u_int cpu = 0; cpu < (mpsafe ? ncpu : 1); cpu++) { local in function:imx7gpc_unmask
195 GPC_IMRn_COREx(reg, cpu));
[all...] |
| /src/sys/arch/arm/sunxi/ |
| sunxi_mc_smp.c | 43 #include <arm/cpu.h>
57 #define PRCM_CL_PWR_CLAMP(cluster, cpu) (0x140 + (cluster) * 0x10 + (cpu) * 0x4)
71 #define CPUXCFG_CL_RST_ETM_RST(cpu) __BIT(20 + (cpu))
72 #define CPUXCFG_CL_RST_DBG_RST(cpu) __BIT(16 + (cpu))
75 #define CPUXCFG_CL_RST_CX_RST(cpu) __BIT(4 + (cpu))
115 bus_space_handle_t cpuxcfg, u_int cluster, u_int cpu, enum sunxi_mc_soc soc
209 const u_int cpu = __SHIFTOUT(mpidr, MPIDR_AFF0); local in function:sun8i_a83t_smp_enable
243 const u_int cpu = __SHIFTOUT(mpidr, MPIDR_AFF0); local in function:sun9i_a80_smp_enable
[all...] |
| /src/sys/arch/mips/cavium/ |
| octeon_cpunode.c | 43 #include <sys/cpu.h>
139 .cnaa_name = "cpu",
219 // First thing is setup the exception vectors for this cpu.
222 // Next rewrite those exceptions to use this cpu's cpu_info.
252 struct cpu_softc * const cpu __diagused = ci->ci_softc;
257 KASSERTMSG(cpu != NULL, "ci %p index %d", ci, cpu_index(ci));
272 cpu->cpu_wdog_sih = softint_establish(SOFTINT_CLOCK|SOFTINT_MPSAFE,
273 wdog_cpunode_poke, cpu);
274 KASSERT(cpu->cpu_wdog_sih != NULL);
372 struct cpu_softc * const cpu = ci->ci_softc local in function:wdog_cpunode_setmode
403 struct cpu_softc * const cpu = ci->ci_softc; local in function:wdog_cpunode_setmode
422 struct cpu_softc *cpu = arg; local in function:wdog_cpunode_poke
[all...] |
| octeon_intr.c | 50 #include <sys/cpu.h>
220 struct cpu_softc *cpu; local in function:octeon_intr_setup
226 cpu = &octeon_cpu_softc[cpunum];
228 cpu->cpu_ip2_sum0 = X(CIU_IP2_SUM0(cpunum));
229 cpu->cpu_ip3_sum0 = X(CIU_IP3_SUM0(cpunum));
230 cpu->cpu_ip4_sum0 = X(CIU_IP4_SUM0(cpunum));
232 cpu->cpu_int_sum1 = X(CIU_INT_SUM1);
234 cpu->cpu_ip2_en[0] = X(CIU_IP2_EN0(cpunum));
235 cpu->cpu_ip3_en[0] = X(CIU_IP3_EN0(cpunum));
236 cpu->cpu_ip4_en[0] = X(CIU_IP4_EN0(cpunum))
259 struct cpu_softc *cpu = &octeon_cpu_softc[cpunum]; local in function:octeon_intr_init
338 struct cpu_softc *cpu; local in function:octeon_intr_establish
423 struct cpu_softc *cpu; local in function:octeon_intr_disestablish
481 struct cpu_softc * const cpu = ci->ci_softc; local in function:octeon_iointr
541 struct cpu_softc * const cpu = ci->ci_softc; local in function:octeon_ipi_intr
601 struct cpu_softc * const cpu = ci->ci_softc; local in function:octeon_send_ipi
[all...] |
| /src/sys/arch/x86/pci/ |
| amdtemp.c | 54 #include <sys/cpu.h>
126 } cpu[5]; member in struct:__anon9c885a410108
225 aprint_normal(": AMD CPU Temperature Sensors");
363 for (j = 0; amdtemp_core[i].cpu[j].cpuid != 0; j++) {
365 != amdtemp_core[i].cpu[j].cpuid)
373 switch (amdtemp_core[i].cpu[j].socket) {
412 * There are two sensors per CPU core. So we use the device unit as
423 "CPU%u Sensor%u", dv_unit + (i / 2), i % 2);
495 "cpu%u temperature", dv_unit);
|
| /src/sys/dev/i2c/ |
| ibmhawkreg.h | 60 uint8_t cpu[IBMHAWK_MAX_CPU]; member in struct:ibmhawk_response::__anonb95b376d0408
65 #define ihr_t_cpu resp_temp.cpu
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/selftests/ |
| i915_gem_coherency.c | 32 u32 *cpu; local in function:cpu_set
41 cpu = map + offset_in_page(offset);
44 drm_clflush_virt_range(cpu, sizeof(*cpu));
46 *cpu = v;
49 drm_clflush_virt_range(cpu, sizeof(*cpu));
62 u32 *cpu; local in function:cpu_get
71 cpu = map + offset_in_page(offset);
74 drm_clflush_virt_range(cpu, sizeof(*cpu))
[all...] |
