| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rv515.c | 53 static const u32 crtc_offsets[2] = variable in typeref:typename:const u32[2]
315 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
318 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
321 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
323 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
324 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
335 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
336 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
338 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
339 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0)
[all...] |
| radeon_rs600.c | 60 static const u32 crtc_offsets[2] = variable in typeref:typename:const u32[2]
68 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
78 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
79 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
102 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
|
| radeon_r600.c | 107 static const u32 crtc_offsets[2] = variable in typeref:typename:const u32[2]
1627 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1628 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1636 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
|
| radeon_evergreen.c | 120 static const u32 crtc_offsets[6] = variable in typeref:typename:const u32[6]
1358 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
1368 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
1369 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
1392 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
2684 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
2688 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
2691 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2693 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
2694 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0)
[all...] |
| radeon_si.c | 153 static const u32 crtc_offsets[] = variable in typeref:typename:const u32[]
5972 WREG32(INT_MASK + crtc_offsets[i], 0);
5974 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
6126 rdev, INT_MASK + crtc_offsets[i], VBLANK_INT_MASK,
6132 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
6164 grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);
6171 WREG32(GRPH_INT_STATUS + crtc_offsets[j],
6177 WREG32(VBLANK_STATUS + crtc_offsets[j],
6180 WREG32(VLINE_STATUS + crtc_offsets[j],
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gmc_v6_0.c | 70 static const u32 crtc_offsets[6] __unused = variable in typeref:typename:const u32[6]__unused
|
| amdgpu_dce_v10_0.c | 58 static const u32 crtc_offsets[] = variable in typeref:typename:const u32[]
209 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
271 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
272 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
425 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
427 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
435 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
496 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
499 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
500 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i])
[all...] |
| amdgpu_dce_v11_0.c | 58 static const u32 crtc_offsets[] = variable in typeref:typename:const u32[]
227 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
289 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
290 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
441 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
443 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
451 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
522 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
525 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
526 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i])
[all...] |
| amdgpu_dce_v6_0.c | 62 static const u32 crtc_offsets[6] = variable in typeref:typename:const u32[6]
161 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
222 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
223 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
392 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
395 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
396 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
398 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
399 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2605 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]
[all...] |
| amdgpu_dce_v8_0.c | 59 static const u32 crtc_offsets[6] = variable in typeref:typename:const u32[6]
157 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
216 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
217 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
359 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
360 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
368 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
436 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
439 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
440 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i])
[all...] |
