| /src/sys/arch/arm/sunxi/ |
| sunxi_nmi.c | 50 /* ctrl_reg */
65 bus_size_t ctrl_reg; member in struct:sunxi_nmi_config
72 .ctrl_reg = 0x00,
79 .ctrl_reg = 0x0c,
86 .ctrl_reg = 0x00,
152 val = NMI_READ(sc, sc->sc_config->ctrl_reg);
155 NMI_WRITE(sc, sc->sc_config->ctrl_reg, val);
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| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| vlv_dsi.c | 136 i915_reg_t data_reg, ctrl_reg; local in function:intel_dsi_host_transfer
149 ctrl_reg = MIPI_LP_GEN_CTRL(port);
154 ctrl_reg = MIPI_HS_GEN_CTRL(port);
177 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
985 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? local in function:intel_dsi_get_hw_state
987 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
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| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_engine_types.h | 172 bus_size_t ctrl_reg; member in struct:intel_engine_execlists
182 * @ctrl_reg: the enhanced execlists control register, used to load the
185 u32 __iomem *ctrl_reg; member in struct:intel_engine_execlists
|
| /src/sys/dev/ic/ |
| advlib.c | 1460 u_int8_t ctrl_reg; local in function:AscISR
1469 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh);
1470 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET |
1499 (ctrl_reg & ASC_CC_SINGLE_STEP)) {
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| cmd_parser.c | 1204 i915_reg_t ctrl_reg; member in struct:mi_display_flip_command_info
1250 info->ctrl_reg = DSPCNTR(info->pipe);
1254 info->ctrl_reg = SPRCTL(info->pipe);
1316 info->ctrl_reg = DSPCNTR(info->pipe);
1334 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1339 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1363 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1368 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
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