| /src/sys/arch/arm/apple/ |
| apple_mbox.h | 21 uint64_t data0; member in struct:apple_mbox_msg
|
| /src/sys/external/bsd/compiler_rt/dist/lib/tsan/tests/rtl/ |
| tsan_string.cc | 20 char data0[7] = {1, 2, 3, 4, 5, 6, 7}; local in function:__tsan::TEST
22 MainThread().Memcpy(data+1, data0+1, 5);
|
| /src/sys/arch/x86/pci/ |
| fwhrng.c | 74 uint8_t id0, id1, data0, data1; local in function:fwhrng_match
83 data0 = bus_space_read_1(bst, bsh, 0);
93 data0, data1, id0, id1);
96 if ((id0 == data0) && (id1 == data1))
108 data0 = bus_space_read_1(bst, bsh, I82802_RNG_HSR);
110 if ((data0 & I82802_RNG_HSR_PRESENT) == I82802_RNG_HSR_PRESENT)
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/ |
| nouveau_nvkm_subdev_pmu_gt215.c | 36 u32 process, u32 message, u32 data0, u32 data1)
73 nvkm_wr32(device, 0x10a1c4, data0);
99 u32 process, message, data0, data1; local in function:gt215_pmu_recv
116 data0 = nvkm_rd32(device, 0x10a1c4);
128 pmu->recv.data[0] = data0;
145 process, message, data0, data1);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_jpeg_v1_0.c | 379 uint32_t data0, data1, mask; local in function:jpeg_v1_0_decode_ring_emit_vm_flush
384 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
387 jpeg_v1_0_decode_ring_emit_reg_wait(ring, data0, data1, mask);
|
| amdgpu_jpeg_v2_0.c | 633 uint32_t data0, data1, mask; local in function:jpeg_v2_0_dec_ring_emit_vm_flush
638 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
641 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
|
| amdgpu_uvd_v7_0.c | 1381 uint32_t data0, data1, mask; local in function:uvd_v7_0_ring_emit_vm_flush
1386 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1389 uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
|
| amdgpu_vcn.h | 161 unsigned data0; member in struct:amdgpu_vcn_reg
|
| amdgpu_vcn_v1_0.c | 143 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 =
1547 uint32_t data0, data1, mask; local in function:vcn_v1_0_dec_ring_emit_vm_flush
1552 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1555 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
|
| amdgpu_vcn_v2_0.c | 152 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
153 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
1302 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1360 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1369 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1412 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1430 uint32_t data0, data1, mask; local in function:vcn_v2_0_dec_ring_emit_vm_flush
1435 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1438 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1446 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0))
[all...] |
| amdgpu_uvd.c | 98 unsigned data0, data1; member in struct:amdgpu_uvd_cs_ctx
479 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
847 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
926 ctx->data0 = ctx->idx;
|
| /src/sys/arch/hpcarm/dev/ |
| uda1341.c | 95 uint8_t data0; /* direct addressing register */ member in struct:__anonc9cbf1340108
99 uint8_t data0; /* extended addressing register 1 */ member in struct:__anonc9cbf1340208
249 DIRECT_REG.data0 = STATUS0_RST | STATUS0_SC_256 | STATUS0_IF_LSB16;
257 DIRECT_REG.data0 &= ~STATUS0_RST;
268 DIRECT_REG.data0 = STATUS0_SC_256 | STATUS0_IF_LSB16;
272 DIRECT_REG.data0 = STATUS1_OGS | STATUS1_IGS | (1<<7);
277 DIRECT_REG.data0 = DATA0_VC(100) | DATA0_COMMON;
281 DIRECT_REG.data0 = DATA1_BB(0) | DATA1_TR(0) | DATA1_COMMON;
285 DIRECT_REG.data0 = DATA2_PP | DATA2_COMMON;
289 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E0
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/ |
| nouveau_nvkm_engine_gr_ctxgk104.c | 872 u32 data0 = nvkm_rd32(device, 0x17e91c); local in function:gk104_grctx_generate_patch_ltc
875 mmio_wr32(info, 0x17e91c, data0);
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_ioctl.c | 914 void *data0 = data; local in function:drm_ioctl
973 data0 = buf;
980 error = -(*ioctl->func)(dev, data0, file);
984 error = -(*ioctl->func)(dev, data0, file);
990 if (data != data0)
991 memcpy(data, data0, IOCPARM_LEN(cmd));
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_uvd.c | 580 int data0, int data1,
590 offset = radeon_get_ib_value(p, data0);
603 p->ib.ptr[data0] = start & 0xFFFFFFFF;
657 int *data0, int *data1,
667 *data0 = p->idx;
673 r = radeon_uvd_cs_reloc(p, *data0, *data1,
694 int r, data0 = 0, data1 = 0; local in function:radeon_uvd_cs_parse
725 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
|
| /src/sys/arch/sparc64/sparc64/ |
| db_interface.c | 489 unsigned long long i, j, k, data0, data1; local in function:db_dump_pmap
505 data0 = ldxa((vaddr_t)&ptbl[j], ASI_PHYS_CACHED);
508 if (!data0 && !data1) {
513 data0);
|
| /src/sys/dev/ic/ |
| rtsx.c | 980 uint8_t data0; local in function:rtsx_read_phy
995 RTSX_READ(sc, RTSX_PHY_DATA0, &data0);
997 *val = data0 | (data1 << 8);
1029 uint8_t data0, data1, data2, data3, rwctl; local in function:rtsx_read_cfg
1043 RTSX_READ(sc, RTSX_CFGDATA0, &data0);
1047 *val = ((uint32_t)data3 << 24) | (data2 << 16) | (data1 << 8) | data0;
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| handlers.c | 1431 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); local in function:mailbox_write
1443 if (!*data0)
1444 *data0 = 0x1e1a1100;
1446 *data0 = 0x61514b3d;
1453 if (!*data0)
1454 *data0 = 0x16080707;
1456 *data0 = 0x16161616;
1463 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
1466 *data0 |= 0x1;
1470 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n"
[all...] |
| /src/tests/dev/audio/ |
| audiotest.c | 4119 struct ioctl_while_write_data data0, *data; local in function:DEF
4126 data = &data0;
|
