1 /************************************************************************** 2 * 3 * Copyright 2007 VMware, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29 /** 30 * @file 31 * 32 * Abstract graphics pipe state objects. 33 * 34 * Basic notes: 35 * 1. Want compact representations, so we use bitfields. 36 * 2. Put bitfields before other (GLfloat) fields. 37 * 3. enum bitfields need to be at least one bit extra in size so the most 38 * significant bit is zero. MSVC treats enums as signed so if the high 39 * bit is set, the value will be interpreted as a negative number. 40 * That causes trouble in various places. 41 */ 42 43 44 #ifndef PIPE_STATE_H 45 #define PIPE_STATE_H 46 47 #include "p_compiler.h" 48 #include "p_defines.h" 49 #include "p_format.h" 50 51 52 #ifdef __cplusplus 53 extern "C" { 54 #endif 55 56 struct gl_buffer_object; 57 58 /** 59 * Implementation limits 60 */ 61 #define PIPE_MAX_ATTRIBS 32 62 #define PIPE_MAX_CLIP_PLANES 8 63 #define PIPE_MAX_COLOR_BUFS 8 64 #define PIPE_MAX_CONSTANT_BUFFERS 32 65 #define PIPE_MAX_SAMPLERS 32 66 #define PIPE_MAX_SHADER_INPUTS 80 /* 32 GENERIC + 32 PATCH + 16 others */ 67 #define PIPE_MAX_SHADER_OUTPUTS 80 /* 32 GENERIC + 32 PATCH + 16 others */ 68 #define PIPE_MAX_SHADER_SAMPLER_VIEWS 128 69 #define PIPE_MAX_SHADER_BUFFERS 32 70 #define PIPE_MAX_SHADER_IMAGES 32 71 #define PIPE_MAX_TEXTURE_LEVELS 16 72 #define PIPE_MAX_SO_BUFFERS 4 73 #define PIPE_MAX_SO_OUTPUTS 64 74 #define PIPE_MAX_VIEWPORTS 16 75 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_COUNT 8 76 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_ELEMENT_COUNT 2 77 #define PIPE_MAX_WINDOW_RECTANGLES 8 78 #define PIPE_MAX_SAMPLE_LOCATION_GRID_SIZE 4 79 80 #define PIPE_MAX_HW_ATOMIC_BUFFERS 32 81 #define PIPE_MAX_VERTEX_STREAMS 4 82 83 struct pipe_reference 84 { 85 int32_t count; /* atomic */ 86 }; 87 88 89 90 /** 91 * Primitive (point/line/tri) rasterization info 92 */ 93 struct pipe_rasterizer_state 94 { 95 unsigned flatshade:1; 96 unsigned light_twoside:1; 97 unsigned clamp_vertex_color:1; 98 unsigned clamp_fragment_color:1; 99 unsigned front_ccw:1; 100 unsigned cull_face:2; /**< PIPE_FACE_x */ 101 unsigned fill_front:2; /**< PIPE_POLYGON_MODE_x */ 102 unsigned fill_back:2; /**< PIPE_POLYGON_MODE_x */ 103 unsigned offset_point:1; 104 unsigned offset_line:1; 105 unsigned offset_tri:1; 106 unsigned scissor:1; 107 unsigned poly_smooth:1; 108 unsigned poly_stipple_enable:1; 109 unsigned point_smooth:1; 110 unsigned sprite_coord_mode:1; /**< PIPE_SPRITE_COORD_ */ 111 unsigned point_quad_rasterization:1; /** points rasterized as quads or points */ 112 unsigned point_tri_clip:1; /** large points clipped as tris or points */ 113 unsigned point_size_per_vertex:1; /**< size computed in vertex shader */ 114 unsigned multisample:1; /* XXX maybe more ms state in future */ 115 unsigned no_ms_sample_mask_out:1; 116 unsigned force_persample_interp:1; 117 unsigned line_smooth:1; 118 unsigned line_stipple_enable:1; 119 unsigned line_last_pixel:1; 120 unsigned line_rectangular:1; /** lines rasterized as rectangles or parallelograms */ 121 unsigned conservative_raster_mode:2; /**< PIPE_CONSERVATIVE_RASTER_x */ 122 123 /** 124 * Use the first vertex of a primitive as the provoking vertex for 125 * flat shading. 126 */ 127 unsigned flatshade_first:1; 128 129 unsigned half_pixel_center:1; 130 unsigned bottom_edge_rule:1; 131 132 /* 133 * Conservative rasterization subpixel precision bias in bits 134 */ 135 unsigned subpixel_precision_x:4; 136 unsigned subpixel_precision_y:4; 137 138 /** 139 * When true, rasterization is disabled and no pixels are written. 140 * This only makes sense with the Stream Out functionality. 141 */ 142 unsigned rasterizer_discard:1; 143 144 /** 145 * Exposed by PIPE_CAP_TILE_RASTER_ORDER. When true, 146 * tile_raster_order_increasing_* indicate the order that the rasterizer 147 * should render tiles, to meet the requirements of 148 * GL_MESA_tile_raster_order. 149 */ 150 unsigned tile_raster_order_fixed:1; 151 unsigned tile_raster_order_increasing_x:1; 152 unsigned tile_raster_order_increasing_y:1; 153 154 /** 155 * When false, depth clipping is disabled and the depth value will be 156 * clamped later at the per-pixel level before depth testing. 157 * This depends on PIPE_CAP_DEPTH_CLIP_DISABLE. 158 * 159 * If PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE is unsupported, depth_clip_near 160 * is equal to depth_clip_far. 161 */ 162 unsigned depth_clip_near:1; 163 unsigned depth_clip_far:1; 164 165 /** 166 * When true, depth clamp is enabled. 167 * If PIPE_CAP_DEPTH_CLAMP_ENABLE is unsupported, this is always the inverse 168 * of depth_clip_far. 169 */ 170 unsigned depth_clamp:1; 171 172 /** 173 * When true clip space in the z axis goes from [0..1] (D3D). When false 174 * [-1, 1] (GL). 175 * 176 * NOTE: D3D will always use depth clamping. 177 */ 178 unsigned clip_halfz:1; 179 180 /** 181 * When true do not scale offset_units and use same rules for unorm and 182 * float depth buffers (D3D9). When false use GL/D3D1X behaviour. 183 * This depends on PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED. 184 */ 185 unsigned offset_units_unscaled:1; 186 187 /** 188 * Enable bits for clipping half-spaces. 189 * This applies to both user clip planes and shader clip distances. 190 * Note that if the bound shader exports any clip distances, these 191 * replace all user clip planes, and clip half-spaces enabled here 192 * but not written by the shader count as disabled. 193 */ 194 unsigned clip_plane_enable:PIPE_MAX_CLIP_PLANES; 195 196 unsigned line_stipple_factor:8; /**< [1..256] actually */ 197 unsigned line_stipple_pattern:16; 198 199 /** 200 * Replace the given TEXCOORD inputs with point coordinates, max. 8 inputs. 201 * If TEXCOORD (including PCOORD) are unsupported, replace GENERIC inputs 202 * instead. Max. 9 inputs: 8x GENERIC to emulate TEXCOORD, and 1x GENERIC 203 * to emulate PCOORD. 204 */ 205 uint16_t sprite_coord_enable; /* 0-7: TEXCOORD/GENERIC, 8: PCOORD */ 206 207 float line_width; 208 float point_size; /**< used when no per-vertex size */ 209 float offset_units; 210 float offset_scale; 211 float offset_clamp; 212 float conservative_raster_dilate; 213 }; 214 215 216 struct pipe_poly_stipple 217 { 218 unsigned stipple[32]; 219 }; 220 221 222 struct pipe_viewport_state 223 { 224 float scale[3]; 225 float translate[3]; 226 enum pipe_viewport_swizzle swizzle_x:8; 227 enum pipe_viewport_swizzle swizzle_y:8; 228 enum pipe_viewport_swizzle swizzle_z:8; 229 enum pipe_viewport_swizzle swizzle_w:8; 230 }; 231 232 233 struct pipe_scissor_state 234 { 235 unsigned minx:16; 236 unsigned miny:16; 237 unsigned maxx:16; 238 unsigned maxy:16; 239 }; 240 241 242 struct pipe_clip_state 243 { 244 float ucp[PIPE_MAX_CLIP_PLANES][4]; 245 }; 246 247 /** 248 * A single output for vertex transform feedback. 249 */ 250 struct pipe_stream_output 251 { 252 unsigned register_index:6; /**< 0 to 63 (OUT index) */ 253 unsigned start_component:2; /** 0 to 3 */ 254 unsigned num_components:3; /** 1 to 4 */ 255 unsigned output_buffer:3; /**< 0 to PIPE_MAX_SO_BUFFERS */ 256 unsigned dst_offset:16; /**< offset into the buffer in dwords */ 257 unsigned stream:2; /**< 0 to 3 */ 258 }; 259 260 /** 261 * Stream output for vertex transform feedback. 262 */ 263 struct pipe_stream_output_info 264 { 265 unsigned num_outputs; 266 /** stride for an entire vertex for each buffer in dwords */ 267 uint16_t stride[PIPE_MAX_SO_BUFFERS]; 268 269 /** 270 * Array of stream outputs, in the order they are to be written in. 271 * Selected components are tightly packed into the output buffer. 272 */ 273 struct pipe_stream_output output[PIPE_MAX_SO_OUTPUTS]; 274 }; 275 276 /** 277 * The 'type' parameter identifies whether the shader state contains TGSI 278 * tokens, etc. If the driver returns 'PIPE_SHADER_IR_TGSI' for the 279 * 'PIPE_SHADER_CAP_PREFERRED_IR' shader param, the ir will *always* be 280 * 'PIPE_SHADER_IR_TGSI' and the tokens ptr will be valid. If the driver 281 * requests a different 'pipe_shader_ir' type, then it must check the 'type' 282 * enum to see if it is getting TGSI tokens or its preferred IR. 283 * 284 * TODO pipe_compute_state should probably get similar treatment to handle 285 * multiple IR's in a cleaner way.. 286 * 287 * NOTE: since it is expected that the consumer will want to perform 288 * additional passes on the nir_shader, the driver takes ownership of 289 * the nir_shader. If gallium frontends need to hang on to the IR (for 290 * example, variant management), it should use nir_shader_clone(). 291 */ 292 struct pipe_shader_state 293 { 294 enum pipe_shader_ir type; 295 /* TODO move tokens into union. */ 296 const struct tgsi_token *tokens; 297 union { 298 void *native; 299 void *nir; 300 } ir; 301 struct pipe_stream_output_info stream_output; 302 }; 303 304 static inline void 305 pipe_shader_state_from_tgsi(struct pipe_shader_state *state, 306 const struct tgsi_token *tokens) 307 { 308 state->type = PIPE_SHADER_IR_TGSI; 309 state->tokens = tokens; 310 memset(&state->stream_output, 0, sizeof(state->stream_output)); 311 } 312 313 314 struct pipe_stencil_state 315 { 316 unsigned enabled:1; /**< stencil[0]: stencil enabled, stencil[1]: two-side enabled */ 317 unsigned func:3; /**< PIPE_FUNC_x */ 318 unsigned fail_op:3; /**< PIPE_STENCIL_OP_x */ 319 unsigned zpass_op:3; /**< PIPE_STENCIL_OP_x */ 320 unsigned zfail_op:3; /**< PIPE_STENCIL_OP_x */ 321 unsigned valuemask:8; 322 unsigned writemask:8; 323 }; 324 325 326 struct pipe_depth_stencil_alpha_state 327 { 328 struct pipe_stencil_state stencil[2]; /**< [0] = front, [1] = back */ 329 330 unsigned alpha_enabled:1; /**< alpha test enabled? */ 331 unsigned alpha_func:3; /**< PIPE_FUNC_x */ 332 333 unsigned depth_enabled:1; /**< depth test enabled? */ 334 unsigned depth_writemask:1; /**< allow depth buffer writes? */ 335 unsigned depth_func:3; /**< depth test func (PIPE_FUNC_x) */ 336 unsigned depth_bounds_test:1; /**< depth bounds test enabled? */ 337 338 float alpha_ref_value; /**< reference value */ 339 double depth_bounds_min; /**< minimum depth bound */ 340 double depth_bounds_max; /**< maximum depth bound */ 341 }; 342 343 344 struct pipe_rt_blend_state 345 { 346 unsigned blend_enable:1; 347 348 unsigned rgb_func:3; /**< PIPE_BLEND_x */ 349 unsigned rgb_src_factor:5; /**< PIPE_BLENDFACTOR_x */ 350 unsigned rgb_dst_factor:5; /**< PIPE_BLENDFACTOR_x */ 351 352 unsigned alpha_func:3; /**< PIPE_BLEND_x */ 353 unsigned alpha_src_factor:5; /**< PIPE_BLENDFACTOR_x */ 354 unsigned alpha_dst_factor:5; /**< PIPE_BLENDFACTOR_x */ 355 356 unsigned colormask:4; /**< bitmask of PIPE_MASK_R/G/B/A */ 357 }; 358 359 360 struct pipe_blend_state 361 { 362 unsigned independent_blend_enable:1; 363 unsigned logicop_enable:1; 364 unsigned logicop_func:4; /**< PIPE_LOGICOP_x */ 365 unsigned dither:1; 366 unsigned alpha_to_coverage:1; 367 unsigned alpha_to_coverage_dither:1; 368 unsigned alpha_to_one:1; 369 unsigned max_rt:3; /* index of max rt, Ie. # of cbufs minus 1 */ 370 unsigned advanced_blend_func:4; 371 struct pipe_rt_blend_state rt[PIPE_MAX_COLOR_BUFS]; 372 }; 373 374 375 struct pipe_blend_color 376 { 377 float color[4]; 378 }; 379 380 381 struct pipe_stencil_ref 382 { 383 ubyte ref_value[2]; 384 }; 385 386 387 /** 388 * Note that pipe_surfaces are "texture views for rendering" 389 * and so in the case of ARB_framebuffer_no_attachment there 390 * is no pipe_surface state available such that we may 391 * extract the number of samples and layers. 392 */ 393 struct pipe_framebuffer_state 394 { 395 uint16_t width, height; 396 uint16_t layers; /**< Number of layers in a no-attachment framebuffer */ 397 ubyte samples; /**< Number of samples in a no-attachment framebuffer */ 398 399 /** multiple color buffers for multiple render targets */ 400 ubyte nr_cbufs; 401 struct pipe_surface *cbufs[PIPE_MAX_COLOR_BUFS]; 402 403 struct pipe_surface *zsbuf; /**< Z/stencil buffer */ 404 }; 405 406 407 /** 408 * Texture sampler state. 409 */ 410 struct pipe_sampler_state 411 { 412 unsigned wrap_s:3; /**< PIPE_TEX_WRAP_x */ 413 unsigned wrap_t:3; /**< PIPE_TEX_WRAP_x */ 414 unsigned wrap_r:3; /**< PIPE_TEX_WRAP_x */ 415 unsigned min_img_filter:1; /**< PIPE_TEX_FILTER_x */ 416 unsigned min_mip_filter:2; /**< PIPE_TEX_MIPFILTER_x */ 417 unsigned mag_img_filter:1; /**< PIPE_TEX_FILTER_x */ 418 unsigned compare_mode:1; /**< PIPE_TEX_COMPARE_x */ 419 unsigned compare_func:3; /**< PIPE_FUNC_x */ 420 unsigned normalized_coords:1; /**< Are coords normalized to [0,1]? */ 421 unsigned max_anisotropy:5; 422 unsigned seamless_cube_map:1; 423 unsigned border_color_is_integer:1; 424 unsigned reduction_mode:2; /**< PIPE_TEX_REDUCTION_x */ 425 unsigned pad:5; /**< take bits from this for new members */ 426 float lod_bias; /**< LOD/lambda bias */ 427 float min_lod, max_lod; /**< LOD clamp range, after bias */ 428 union pipe_color_union border_color; 429 }; 430 431 union pipe_surface_desc { 432 struct { 433 unsigned level; 434 unsigned first_layer:16; 435 unsigned last_layer:16; 436 } tex; 437 struct { 438 unsigned first_element; 439 unsigned last_element; 440 } buf; 441 }; 442 443 /** 444 * A view into a texture that can be bound to a color render target / 445 * depth stencil attachment point. 446 */ 447 struct pipe_surface 448 { 449 struct pipe_reference reference; 450 enum pipe_format format:16; 451 unsigned writable:1; /**< writable shader resource */ 452 struct pipe_resource *texture; /**< resource into which this is a view */ 453 struct pipe_context *context; /**< context this surface belongs to */ 454 455 /* XXX width/height should be removed */ 456 uint16_t width; /**< logical width in pixels */ 457 uint16_t height; /**< logical height in pixels */ 458 459 /** 460 * Number of samples for the surface. This will be 0 if rendering 461 * should use the resource's nr_samples, or another value if the resource 462 * is bound using FramebufferTexture2DMultisampleEXT. 463 */ 464 unsigned nr_samples:8; 465 466 union pipe_surface_desc u; 467 }; 468 469 470 /** 471 * A view into a texture that can be bound to a shader stage. 472 */ 473 struct pipe_sampler_view 474 { 475 /* Put the refcount on its own cache line to prevent "False sharing". */ 476 EXCLUSIVE_CACHELINE(struct pipe_reference reference); 477 478 enum pipe_format format:15; /**< typed PIPE_FORMAT_x */ 479 enum pipe_texture_target target:5; /**< PIPE_TEXTURE_x */ 480 unsigned swizzle_r:3; /**< PIPE_SWIZZLE_x for red component */ 481 unsigned swizzle_g:3; /**< PIPE_SWIZZLE_x for green component */ 482 unsigned swizzle_b:3; /**< PIPE_SWIZZLE_x for blue component */ 483 unsigned swizzle_a:3; /**< PIPE_SWIZZLE_x for alpha component */ 484 struct pipe_resource *texture; /**< texture into which this is a view */ 485 struct pipe_context *context; /**< context this view belongs to */ 486 union { 487 struct { 488 unsigned first_layer:16; /**< first layer to use for array textures */ 489 unsigned last_layer:16; /**< last layer to use for array textures */ 490 unsigned first_level:8; /**< first mipmap level to use */ 491 unsigned last_level:8; /**< last mipmap level to use */ 492 } tex; 493 struct { 494 unsigned offset; /**< offset in bytes */ 495 unsigned size; /**< size of the readable sub-range in bytes */ 496 } buf; 497 } u; 498 }; 499 500 501 /** 502 * A description of a buffer or texture image that can be bound to a shader 503 * stage. 504 */ 505 struct pipe_image_view 506 { 507 struct pipe_resource *resource; /**< resource into which this is a view */ 508 enum pipe_format format; /**< typed PIPE_FORMAT_x */ 509 uint16_t access; /**< PIPE_IMAGE_ACCESS_x */ 510 uint16_t shader_access; /**< PIPE_IMAGE_ACCESS_x */ 511 512 union { 513 struct { 514 unsigned first_layer:16; /**< first layer to use for array textures */ 515 unsigned last_layer:16; /**< last layer to use for array textures */ 516 unsigned level:8; /**< mipmap level to use */ 517 } tex; 518 struct { 519 unsigned offset; /**< offset in bytes */ 520 unsigned size; /**< size of the accessible sub-range in bytes */ 521 } buf; 522 } u; 523 }; 524 525 526 /** 527 * Subregion of 1D/2D/3D image resource. 528 */ 529 struct pipe_box 530 { 531 /* Fields only used by textures use int16_t instead of int. 532 * x and width are used by buffers, so they need the full 32-bit range. 533 */ 534 int x; 535 int16_t y; 536 int16_t z; 537 int width; 538 int16_t height; 539 int16_t depth; 540 }; 541 542 543 /** 544 * A memory object/resource such as a vertex buffer or texture. 545 */ 546 struct pipe_resource 547 { 548 /* Put the refcount on its own cache line to prevent "False sharing". */ 549 EXCLUSIVE_CACHELINE(struct pipe_reference reference); 550 551 unsigned width0; /**< Used by both buffers and textures. */ 552 uint16_t height0; /* Textures: The maximum height/depth/array_size is 16k. */ 553 uint16_t depth0; 554 uint16_t array_size; 555 556 enum pipe_format format:16; /**< PIPE_FORMAT_x */ 557 enum pipe_texture_target target:8; /**< PIPE_TEXTURE_x */ 558 unsigned last_level:8; /**< Index of last mipmap level present/defined */ 559 560 /** Number of samples determining quality, driving rasterizer, shading, 561 * and framebuffer. 562 */ 563 unsigned nr_samples:8; 564 565 /** Multiple samples within a pixel can have the same value. 566 * nr_storage_samples determines how many slots for different values 567 * there are per pixel. Only color buffers can set this lower than 568 * nr_samples. 569 */ 570 unsigned nr_storage_samples:8; 571 572 unsigned usage:8; /**< PIPE_USAGE_x (not a bitmask) */ 573 unsigned bind; /**< bitmask of PIPE_BIND_x */ 574 unsigned flags; /**< bitmask of PIPE_RESOURCE_FLAG_x */ 575 576 /** 577 * For planar images, ie. YUV EGLImage external, etc, pointer to the 578 * next plane. 579 */ 580 struct pipe_resource *next; 581 /* The screen pointer should be last for optimal structure packing. */ 582 struct pipe_screen *screen; /**< screen that this texture belongs to */ 583 }; 584 585 /** 586 * Opaque object used for separate resource/memory allocations. 587 */ 588 struct pipe_memory_allocation; 589 590 /** 591 * Transfer object. For data transfer to/from a resource. 592 */ 593 struct pipe_transfer 594 { 595 struct pipe_resource *resource; /**< resource to transfer to/from */ 596 enum pipe_map_flags usage:24; 597 unsigned level:8; /**< texture mipmap level */ 598 struct pipe_box box; /**< region of the resource to access */ 599 unsigned stride; /**< row stride in bytes */ 600 unsigned layer_stride; /**< image/layer stride in bytes */ 601 602 /* Offset into a driver-internal staging buffer to make use of unused 603 * padding in this structure. 604 */ 605 unsigned offset; 606 }; 607 608 609 /** 610 * A vertex buffer. Typically, all the vertex data/attributes for 611 * drawing something will be in one buffer. But it's also possible, for 612 * example, to put colors in one buffer and texcoords in another. 613 */ 614 struct pipe_vertex_buffer 615 { 616 uint16_t stride; /**< stride to same attrib in next vertex, in bytes */ 617 bool is_user_buffer; 618 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */ 619 620 union { 621 struct pipe_resource *resource; /**< the actual buffer */ 622 const void *user; /**< pointer to a user buffer */ 623 } buffer; 624 }; 625 626 627 /** 628 * A constant buffer. A subrange of an existing buffer can be set 629 * as a constant buffer. 630 */ 631 struct pipe_constant_buffer 632 { 633 struct pipe_resource *buffer; /**< the actual buffer */ 634 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */ 635 unsigned buffer_size; /**< how much data can be read in shader */ 636 const void *user_buffer; /**< pointer to a user buffer if buffer == NULL */ 637 }; 638 639 640 /** 641 * An untyped shader buffer supporting loads, stores, and atomics. 642 */ 643 struct pipe_shader_buffer { 644 struct pipe_resource *buffer; /**< the actual buffer */ 645 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */ 646 unsigned buffer_size; /**< how much data can be read in shader */ 647 }; 648 649 650 /** 651 * A stream output target. The structure specifies the range vertices can 652 * be written to. 653 * 654 * In addition to that, the structure should internally maintain the offset 655 * into the buffer, which should be incremented everytime something is written 656 * (appended) to it. The internal offset is buffer_offset + how many bytes 657 * have been written. The internal offset can be stored on the device 658 * and the CPU actually doesn't have to query it. 659 * 660 * Note that the buffer_size variable is actually specifying the available 661 * space in the buffer, not the size of the attached buffer. 662 * In other words in majority of cases buffer_size would simply be 663 * 'buffer->width0 - buffer_offset', so buffer_size refers to the size 664 * of the buffer left, after accounting for buffer offset, for stream output 665 * to write to. 666 * 667 * Use PIPE_QUERY_SO_STATISTICS to know how many primitives have 668 * actually been written. 669 */ 670 struct pipe_stream_output_target 671 { 672 struct pipe_reference reference; 673 struct pipe_resource *buffer; /**< the output buffer */ 674 struct pipe_context *context; /**< context this SO target belongs to */ 675 676 unsigned buffer_offset; /**< offset where data should be written, in bytes */ 677 unsigned buffer_size; /**< how much data is allowed to be written */ 678 }; 679 680 681 /** 682 * Information to describe a vertex attribute (position, color, etc) 683 */ 684 struct pipe_vertex_element 685 { 686 /** Offset of this attribute, in bytes, from the start of the vertex */ 687 uint16_t src_offset; 688 689 /** Which vertex_buffer (as given to pipe->set_vertex_buffer()) does 690 * this attribute live in? 691 */ 692 uint8_t vertex_buffer_index:7; 693 694 /** 695 * Whether this element refers to a dual-slot vertex shader input. 696 * The purpose of this field is to do dual-slot lowering when the CSO is 697 * created instead of during every state change. 698 * 699 * It's lowered by util_lower_uint64_vertex_elements. 700 */ 701 bool dual_slot:1; 702 703 /** 704 * This has only 8 bits because all vertex formats should be <= 255. 705 */ 706 uint8_t src_format; /* low 8 bits of enum pipe_format. */ 707 708 /** Instance data rate divisor. 0 means this is per-vertex data, 709 * n means per-instance data used for n consecutive instances (n > 0). 710 */ 711 unsigned instance_divisor; 712 }; 713 714 /** 715 * Opaque refcounted constant state object encapsulating a vertex buffer, 716 * index buffer, and vertex elements. Used by display lists to bind those 717 * states and pass buffer references quickly. 718 * 719 * The state contains 1 index buffer, 0 or 1 vertex buffer, and 0 or more 720 * vertex elements. 721 * 722 * Constraints on the buffers to get the fastest codepath: 723 * - All buffer contents are considered immutable and read-only after 724 * initialization. This implies the following things. 725 * - No place is required to track whether these buffers are busy. 726 * - All CPU mappings of these buffers can be forced to UNSYNCHRONIZED by 727 * both drivers and common code unconditionally. 728 * - Buffer invalidation can be skipped by both drivers and common code 729 * unconditionally. 730 */ 731 struct pipe_vertex_state { 732 struct pipe_reference reference; 733 struct pipe_screen *screen; 734 735 /* The following structure is used as a key for util_vertex_state_cache 736 * to deduplicate identical state objects and thus enable more 737 * opportunities for draw merging. 738 */ 739 struct { 740 struct pipe_resource *indexbuf; 741 struct pipe_vertex_buffer vbuffer; 742 unsigned num_elements; 743 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 744 uint32_t full_velem_mask; 745 } input; 746 }; 747 748 struct pipe_draw_indirect_info 749 { 750 unsigned offset; /**< must be 4 byte aligned */ 751 unsigned stride; /**< must be 4 byte aligned */ 752 unsigned draw_count; /**< number of indirect draws */ 753 unsigned indirect_draw_count_offset; /**< must be 4 byte aligned */ 754 755 /* Indirect draw parameters resource is laid out as follows: 756 * 757 * if using indexed drawing: 758 * struct { 759 * uint32_t count; 760 * uint32_t instance_count; 761 * uint32_t start; 762 * int32_t index_bias; 763 * uint32_t start_instance; 764 * }; 765 * otherwise: 766 * struct { 767 * uint32_t count; 768 * uint32_t instance_count; 769 * uint32_t start; 770 * uint32_t start_instance; 771 * }; 772 * 773 * If NULL, count_from_stream_output != NULL. 774 */ 775 struct pipe_resource *buffer; 776 777 /* Indirect draw count resource: If not NULL, contains a 32-bit value which 778 * is to be used as the real draw_count. 779 */ 780 struct pipe_resource *indirect_draw_count; 781 782 /** 783 * Stream output target. If not NULL, it's used to provide the 'count' 784 * parameter based on the number vertices captured by the stream output 785 * stage. (or generally, based on the number of bytes captured) 786 * 787 * Only 'mode', 'start_instance', and 'instance_count' are taken into 788 * account, all the other variables from pipe_draw_info are ignored. 789 * 790 * 'start' is implicitly 0 and 'count' is set as discussed above. 791 * The draw command is non-indexed. 792 * 793 * Note that this only provides the count. The vertex buffers must 794 * be set via set_vertex_buffers manually. 795 */ 796 struct pipe_stream_output_target *count_from_stream_output; 797 }; 798 799 struct pipe_draw_start_count_bias { 800 unsigned start; 801 unsigned count; 802 int index_bias; /**< a bias to be added to each index */ 803 }; 804 805 /** 806 * Draw vertex state description. It's translated to pipe_draw_info as follows: 807 * - mode comes from this structure 808 * - index_size is 4 809 * - instance_count is 1 810 * - index.resource comes from pipe_vertex_state 811 * - everything else is 0 812 */ 813 struct pipe_draw_vertex_state_info { 814 #if defined(__GNUC__) 815 /* sizeof(mode) == 1 because it's a packed enum. */ 816 enum pipe_prim_type mode; /**< the mode of the primitive */ 817 #else 818 /* sizeof(mode) == 1 is required by draw merging in u_threaded_context. */ 819 uint8_t mode; /**< the mode of the primitive */ 820 #endif 821 bool take_vertex_state_ownership; /**< for skipping reference counting */ 822 }; 823 824 /** 825 * Information to describe a draw_vbo call. 826 */ 827 struct pipe_draw_info 828 { 829 #if defined(__GNUC__) 830 /* sizeof(mode) == 1 because it's a packed enum. */ 831 enum pipe_prim_type mode; /**< the mode of the primitive */ 832 #else 833 /* sizeof(mode) == 1 is required by draw merging in u_threaded_context. */ 834 uint8_t mode; /**< the mode of the primitive */ 835 #endif 836 uint8_t index_size; /**< if 0, the draw is not indexed. */ 837 uint8_t view_mask; /**< mask of multiviews for this draw */ 838 bool primitive_restart:1; 839 bool has_user_indices:1; /**< if true, use index.user_buffer */ 840 bool index_bounds_valid:1; /**< whether min_index and max_index are valid; 841 they're always invalid if index_size == 0 */ 842 bool increment_draw_id:1; /**< whether drawid increments for direct draws */ 843 bool take_index_buffer_ownership:1; /**< callee inherits caller's refcount 844 (no need to reference indexbuf, but still needs to unreference it) */ 845 bool index_bias_varies:1; /**< true if index_bias varies between draws */ 846 uint8_t _pad:2; 847 848 unsigned start_instance; /**< first instance id */ 849 unsigned instance_count; /**< number of instances */ 850 851 /** 852 * Primitive restart enable/index (only applies to indexed drawing) 853 */ 854 unsigned restart_index; 855 856 /* Pointers must be placed appropriately for optimal structure packing on 857 * 64-bit CPUs. 858 */ 859 860 /** 861 * An index buffer. When an index buffer is bound, all indices to vertices 862 * will be looked up from the buffer. 863 * 864 * If has_user_indices, use index.user, else use index.resource. 865 */ 866 union { 867 struct pipe_resource *resource; /**< real buffer */ 868 struct gl_buffer_object *gl_bo; /**< for the GL frontend, not passed to drivers */ 869 const void *user; /**< pointer to a user buffer */ 870 } index; 871 872 /* These must be last for better packing in u_threaded_context. */ 873 unsigned min_index; /**< the min index */ 874 unsigned max_index; /**< the max index */ 875 }; 876 877 878 /** 879 * Information to describe a blit call. 880 */ 881 struct pipe_blit_info 882 { 883 struct { 884 struct pipe_resource *resource; 885 unsigned level; 886 struct pipe_box box; /**< negative width, height only legal for src */ 887 /* For pipe_surface-like format casting: */ 888 enum pipe_format format; /**< must be supported for sampling (src) 889 or rendering (dst), ZS is always supported */ 890 } dst, src; 891 892 unsigned mask; /**< bitmask of PIPE_MASK_R/G/B/A/Z/S */ 893 unsigned filter; /**< PIPE_TEX_FILTER_* */ 894 bool sample0_only; 895 bool scissor_enable; 896 struct pipe_scissor_state scissor; 897 898 /* Window rectangles can either be inclusive or exclusive. */ 899 bool window_rectangle_include; 900 unsigned num_window_rectangles; 901 struct pipe_scissor_state window_rectangles[PIPE_MAX_WINDOW_RECTANGLES]; 902 903 bool render_condition_enable; /**< whether the blit should honor the 904 current render condition */ 905 bool alpha_blend; /* dst.rgb = src.rgb * src.a + dst.rgb * (1 - src.a) */ 906 bool is_dri_blit_image; 907 }; 908 909 /** 910 * Information to describe a launch_grid call. 911 */ 912 struct pipe_grid_info 913 { 914 /** 915 * For drivers that use PIPE_SHADER_IR_NATIVE as their prefered IR, this 916 * value will be the index of the kernel in the opencl.kernels metadata 917 * list. 918 */ 919 uint32_t pc; 920 921 /** 922 * Will be used to initialize the INPUT resource, and it should point to a 923 * buffer of at least pipe_compute_state::req_input_mem bytes. 924 */ 925 void *input; 926 927 /** 928 * Grid number of dimensions, 1-3, e.g. the work_dim parameter passed to 929 * clEnqueueNDRangeKernel. Note block[] and grid[] must be padded with 930 * 1 for non-used dimensions. 931 */ 932 uint work_dim; 933 934 /** 935 * Determine the layout of the working block (in thread units) to be used. 936 */ 937 uint block[3]; 938 939 /** 940 * last_block allows disabling threads at the farthermost grid boundary. 941 * Full blocks as specified by "block" are launched, but the threads 942 * outside of "last_block" dimensions are disabled. 943 * 944 * If a block touches the grid boundary in the i-th axis, threads with 945 * THREAD_ID[i] >= last_block[i] are disabled. 946 * 947 * If last_block[i] is 0, it has the same behavior as last_block[i] = block[i], 948 * meaning no effect. 949 * 950 * It's equivalent to doing this at the beginning of the compute shader: 951 * 952 * for (i = 0; i < 3; i++) { 953 * if (block_id[i] == grid[i] - 1 && 954 * last_block[i] && thread_id[i] >= last_block[i]) 955 * return; 956 * } 957 */ 958 uint last_block[3]; 959 960 /** 961 * Determine the layout of the grid (in block units) to be used. 962 */ 963 uint grid[3]; 964 965 /** 966 * Base offsets to launch grids from 967 */ 968 uint grid_base[3]; 969 970 /* Indirect compute parameters resource: If not NULL, block sizes are taken 971 * from this buffer instead, which is laid out as follows: 972 * 973 * struct { 974 * uint32_t num_blocks_x; 975 * uint32_t num_blocks_y; 976 * uint32_t num_blocks_z; 977 * }; 978 */ 979 struct pipe_resource *indirect; 980 unsigned indirect_offset; /**< must be 4 byte aligned */ 981 }; 982 983 /** 984 * Structure used as a header for serialized compute programs. 985 */ 986 struct pipe_binary_program_header 987 { 988 uint32_t num_bytes; /**< Number of bytes in the LLVM bytecode program. */ 989 char blob[]; 990 }; 991 992 struct pipe_compute_state 993 { 994 enum pipe_shader_ir ir_type; /**< IR type contained in prog. */ 995 const void *prog; /**< Compute program to be executed. */ 996 unsigned req_local_mem; /**< Required size of the LOCAL resource. */ 997 unsigned req_private_mem; /**< Required size of the PRIVATE resource. */ 998 unsigned req_input_mem; /**< Required size of the INPUT resource. */ 999 }; 1000 1001 /** 1002 * Structure that contains a callback for debug messages from the driver back 1003 * to the gallium frontend. 1004 */ 1005 struct pipe_debug_callback 1006 { 1007 /** 1008 * When set to \c true, the callback may be called asynchronously from a 1009 * driver-created thread. 1010 */ 1011 bool async; 1012 1013 /** 1014 * Callback for the driver to report debug/performance/etc information back 1015 * to the gallium frontend. 1016 * 1017 * \param data user-supplied data pointer 1018 * \param id message type identifier, if pointed value is 0, then a 1019 * new id is assigned 1020 * \param type PIPE_DEBUG_TYPE_* 1021 * \param format printf-style format string 1022 * \param args args for format string 1023 */ 1024 void (*debug_message)(void *data, 1025 unsigned *id, 1026 enum pipe_debug_type type, 1027 const char *fmt, 1028 va_list args); 1029 void *data; 1030 }; 1031 1032 /** 1033 * Structure that contains a callback for device reset messages from the driver 1034 * back to the gallium frontend. 1035 * 1036 * The callback must not be called from driver-created threads. 1037 */ 1038 struct pipe_device_reset_callback 1039 { 1040 /** 1041 * Callback for the driver to report when a device reset is detected. 1042 * 1043 * \param data user-supplied data pointer 1044 * \param status PIPE_*_RESET 1045 */ 1046 void (*reset)(void *data, enum pipe_reset_status status); 1047 1048 void *data; 1049 }; 1050 1051 /** 1052 * Information about memory usage. All sizes are in kilobytes. 1053 */ 1054 struct pipe_memory_info 1055 { 1056 unsigned total_device_memory; /**< size of device memory, e.g. VRAM */ 1057 unsigned avail_device_memory; /**< free device memory at the moment */ 1058 unsigned total_staging_memory; /**< size of staging memory, e.g. GART */ 1059 unsigned avail_staging_memory; /**< free staging memory at the moment */ 1060 unsigned device_memory_evicted; /**< size of memory evicted (monotonic counter) */ 1061 unsigned nr_device_memory_evictions; /**< # of evictions (monotonic counter) */ 1062 }; 1063 1064 /** 1065 * Structure that contains information about external memory 1066 */ 1067 struct pipe_memory_object 1068 { 1069 bool dedicated; 1070 }; 1071 1072 #ifdef __cplusplus 1073 } 1074 #endif 1075 1076 #endif 1077
Indexes created Wed Jul 22 00:25:13 UTC 2026