| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_cdclk.h | 23 u8 divider; /* CD2X divider * 2 */ member in struct:intel_cdclk_vals
|
| intel_lvds.c | 64 int divider; member in struct:intel_lvds_pps
176 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
201 "divider %d port %d powerdown_on_reset %d\n",
203 pps->divider, pps->port, pps->powerdown_on_reset);
227 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
|
| intel_cdclk.c | 463 * CCK divider into the Punit register.
575 u32 divider; local in function:vlv_set_cdclk
577 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
580 /* adjust cdclk divider */
583 val |= divider;
587 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
1171 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1172 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1173 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1174 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 }
1359 u32 divider; local in function:bxt_get_cdclk
1501 u32 val, divider; local in function:bxt_set_cdclk
2543 int divider, fraction; local in function:cnp_rawclk
[all...] |
| intel_display.c | 210 int divider; local in function:vlv_get_cck_clock
213 divider = val & CCK_FREQUENCY_VALUES;
216 (divider << CCK_FREQUENCY_STATUS_SHIFT),
219 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
388 /* Pineview only has one combined m divider, which we treat as m2. */
573 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
709 * If match_clock is provided, then best_clock P divider must match the P
710 * divider from @match_clock used for LVDS downclocking.
767 * If match_clock is provided, then best_clock P divider must match the P
768 * divider from @match_clock used for LVDS downclocking
[all...] |
| /src/sys/arch/arm/broadcom/ |
| bcm2835_bsc.c | 103 u_int divider = howmany(sc->sc_frequency, sc->sc_clkrate); local in function:bsciic_attach
105 __SHIFTIN(divider, BSC_DIV_CDIV));
|
| /src/sys/dev/marvell/ |
| mvspi.c | 157 uint32_t divider; local in function:mvspi_configure
196 divider = spr * (1 << sppr);
198 if ((mvTclk / divider) > speed)
202 if ((mvTclk / divider) == speed) {
210 if ((speed - (mvTclk / divider)) < min_baud_offset) {
211 min_baud_offset = (speed - (mvTclk / divider));
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_gk20a.c | 97 u32 divider; local in function:gk20a_pllg_calc_rate
100 divider = pll->m * clk->pl_to_div(pll->pl);
102 return rate / divider / 2;
310 /* split VCO-to-bypass jump in half by setting out divider 1:2 */
313 /* Intentional 2nd write to assure linear divider operation */
327 /* restore out divider 1:1 */
331 /* Intentional 2nd write to assure linear divider operation */
|
| /src/sys/arch/arm/nxp/ |
| imx6_ccm.c | 425 u_int divider = uimax(1, rate_parent / rate); local in function:imxccm_clk_set_rate_div
440 if (div->tbl[i] == divider)
448 v |= __SHIFTIN(divider - 1, div->mask);
|
| /src/sys/dev/i2c/ |
| sensirion_voc_algorithm.c | 136 uint32_t divider = (uint32_t)((b >= 0) ? b : (-b)); local in function:fix16_div
142 while (divider < remainder) {
143 divider <<= 1;
152 if (divider & 0x80000000) {
154 // We know that divider's bottom bit is 0 here.
155 if (remainder >= divider) {
157 remainder -= divider;
159 divider >>= 1;
165 if (remainder >= divider) {
167 remainder -= divider;
[all...] |
| /src/sys/dev/pci/ |
| cmpci.c | 303 int divider; member in struct:__anon3999e0510108
332 return cmpci_rate_table[index].divider;
598 DPRINTF(("%s: sample:%u, divider=%d\n",
|
| radeonfb.c | 394 int divider; member in struct:__anon5a2a5ee60308
1669 * ATOM BIOS doesn't supply a reference divider, so we
1719 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) {
1728 * limitation or an error in the divider table.
1739 DPRINTF(("post divider: %d (mask %x)\n", div,
1749 DPRINTF(("feedback divider: %d\n", *feedbackdiv));
2156 * divider.
2250 /* program reference divider */
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_legacy_crtc.c | 770 int divider; member in struct:radeon_set_pll::__anond72bf03f0108
838 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
839 if (post_div->divider == post_divider)
843 if (!post_div->divider)
945 This appears to related to the PLL divider registers (fail to lock?).
991 /* R300 uses ref_div_acc field as real ref divider */
|
| radeon_trinity_dpm.c | 618 u32 index, u32 divider)
625 value |= DS_DIV(divider);
630 u32 index, u32 divider)
637 value |= DS_SH_DIV(divider);
1835 u32 divider; local in function:trinity_convert_did_to_freq
1838 divider = did * 25;
1840 divider = (did - 64) * 50 + 1600;
1842 divider = (did - 96) * 100 + 3200;
1844 divider = 128 * 100;
1848 return ((pi->sys_info.dentist_vco_freq * 100) + (divider - 1)) / divider
[all...] |
| /src/usr.bin/units/ |
| units.c | 347 char *divider, *slash; local in function:addunit
397 divider = strchr(item, '|');
398 if (divider) {
399 *divider = 0;
405 if (endptr != divider) {
414 num = strtod(divider + 1, &endptr);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| opp.h | 241 uint32_t divider; /* (actually HW range is min/divider; divider !=0) */ member in struct:hw_adjustment_range
|
| /src/sys/arch/arm/rockchip/ |
| rk_spi.c | 262 uint16_t divider; local in function:rk_spi_configure
264 divider = (sc->sc_spi_freq / speed) & ~1;
265 if (divider < 2) {
269 divider = 2;
297 SPIREG_WRITE(sc, SPI_BAUDR, divider);
|
