| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/ |
| irq_service.h | 52 uint32_t enable_mask; member in struct:irq_source_info
|
| /src/sys/arch/powerpc/marvell/ |
| pic_discovery.c | 65 #define enable_mask _mask.mask64 macro
108 discovery->enable_mask = 0;
118 discovery->enable_mask |= (1 << irq);
127 discovery->enable_mask &= ~(1 << irq);
|
| /src/sys/arch/macppc/macppc/ |
| pic_ohare.c | 57 uint32_t enable_mask; member in struct:ohare_ops
147 ohare->enable_mask = 0;
170 ohare->enable_mask |= mask;
171 out32rb(INT_ENABLE_REG, ohare->enable_mask);
181 ohare->enable_mask |= mask;
182 out32rb(INT_ENABLE_REG, ohare->enable_mask);
196 ohare->enable_mask &= ~mask;
197 out32rb(INT_ENABLE_REG, ohare->enable_mask);
209 levels = in32rb(INT_LEVEL_REG) & ohare->enable_mask;
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_fifo_underrun.c | 99 u32 enable_mask; local in function:i9xx_check_fifo_underruns
106 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
107 I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
124 u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); local in function:i9xx_set_fifo_underrun_reporting
126 I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
|
| /src/sys/arch/powerpc/pic/ |
| picvar.h | 85 uint32_t enable_mask; member in struct:i8259_ops
|
| /src/sys/external/bsd/drm2/dist/drm/via/ |
| via_drv.h | 73 uint32_t enable_mask; member in struct:drm_via_irq
|
| /src/sys/dev/i2c/ |
| rkpmic.c | 81 uint8_t enable_mask; member in struct:rkpmic_ctrl
102 .enable_reg = 0x23, .enable_mask = __BIT(0),
106 .enable_reg = 0x23, .enable_mask = __BIT(1),
110 .enable_reg = 0x23, .enable_mask = __BIT(2) },
112 .enable_reg = 0x23, .enable_mask = __BIT(3),
118 .enable_reg = 0x27, .enable_mask = __BIT(0),
122 .enable_reg = 0x27, .enable_mask = __BIT(1),
126 .enable_reg = 0x27, .enable_mask = __BIT(2),
140 .enable_reg = 0x23, .enable_mask = __BIT(0),
144 .enable_reg = 0x23, .enable_mask = __BIT(1)
[all...] |
| as3722.c | 136 u_int enable_mask; member in struct:as3722regdef
149 .enable_mask = AS3722_SDCONTROL_SD4_ENABLE,
156 .enable_mask = 0x40,
581 if (!regdef->enable_mask)
587 regdef->enable_mask, 0, flags);
590 0, regdef->enable_mask, flags);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| kv_dpm.h | 94 u32 enable_mask; member in struct:kv_lcac_config_reg
220 int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask);
|
| amdgpu_kv_dpm.c | 407 local_cac_reg->enable_mask);
2116 u32 enable_mask, i; local in function:kv_force_dpm_highest
2118 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2123 if (enable_mask & (1 << i))
2136 u32 enable_mask, i; local in function:kv_force_dpm_lowest
2138 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2143 if (enable_mask & (1 << i))
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| kv_dpm.h | 68 u32 enable_mask; member in struct:kv_lcac_config_reg
191 int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);
|
| radeon_kv_dpm.c | 280 local_cac_reg->enable_mask);
2050 u32 enable_mask, i; local in function:kv_force_dpm_highest
2052 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
2057 if (enable_mask & (1 << i))
2070 u32 enable_mask, i; local in function:kv_force_dpm_lowest
2072 ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
2077 if (enable_mask & (1 << i))
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_irq.c | 422 u32 enable_mask = status_mask << 16; local in function:i915_pipestat_enable_mask
442 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
446 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
448 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
451 WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
453 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
454 pipe_name(pipe), enable_mask, status_mask);
456 return enable_mask;
463 u32 enable_mask; local in function:i915_enable_pipestat
476 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe)
486 u32 enable_mask; local in function:i915_disable_pipestat
1314 u32 status_mask, enable_mask, iir_bit = 0; local in function:i9xx_pipestat_irq_ack
2732 u32 enable_mask; local in function:vlv_display_irq_postinstall
3500 u16 enable_mask; local in function:i8xx_irq_postinstall
3667 u32 enable_mask; local in function:i915_irq_postinstall
3773 u32 enable_mask; local in function:i965_irq_postinstall
[all...] |
