Searched defs:enum_ref (Results 1 - 9 of 9) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/registers/
H A Dgfx10-rsrc.json335 {"bits": [12, 18], "enum_ref": "GFX10_FORMAT", "name": "FORMAT"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.4
339 {"bits": [28, 29], "enum_ref": "SQ_BUF_RSRC_WORD3__OOB_SELECT", "name": "OOB_SELECT"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.8
349 {"bits": [12, 18], "enum_ref": "GFX10_FORMAT", "name": "FORMAT"}, string in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.4
354 {"bits": [28, 29], "enum_ref": "SQ_BUF_RSRC_WORD3__OOB_SELECT", "name": "OOB_SELECT"}, string in object:register_types.SQ_BUF_RSRC_WORD3_gfx103.fields.9
361 {"bits": [4, 9], "enum_ref": "SQ_EXP_0__TGT", "name": "TGT"}, string in object:register_types.SQ_EXP_0.fields.1
371 {"bits": [20, 28], "enum_ref": "GFX10_FORMAT", "name": "FORMAT"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.2
391 {"bits": [25, 27], "enum_ref": "SQ_IMG_RSRC_WORD3__BC_SWIZZLE", "name": "BC_SWIZZLE"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.7
H A Dpkt3.json267 {"bits": [22, 23], "enum_ref": "COMMAND__SRC_SWAP", "name": "SRC_SWAP"}, string in object:register_types.COMMAND.fields.2
268 {"bits": [24, 25], "enum_ref": "COMMAND__SRC_SWAP", "name": "DST_SWAP"}, string in object:register_types.COMMAND.fields.3
269 {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"}, string in object:register_types.COMMAND.fields.4
270 {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"}, string in object:register_types.COMMAND.fields.5
271 {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"}, string in object:register_types.COMMAND.fields.6
272 {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"}, string in object:register_types.COMMAND.fields.7
279 {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"}, string in object:register_types.COMMAND_gfx9.fields.1
280 {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"}, string in object:register_types.COMMAND_gfx9.fields.2
281 {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"}, string in object:register_types.COMMAND_gfx9.fields.3
282 {"bits": [29, 29], "enum_ref" string in object:register_types.COMMAND_gfx9.fields.4
289 {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL", "name": "DST_SEL"}, string in object:register_types.CONTROL.fields.0
292 {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"} string in object:register_types.CONTROL.fields.3
297 {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL_cik", "name": "DST_SEL"}, string in object:register_types.CONTROL_cik.fields.0
300 {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"} string in object:register_types.CONTROL_cik.fields.3
311 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"}, string in object:register_types.CP_DMA_WORD1.fields.1
312 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, string in object:register_types.CP_DMA_WORD1.fields.2
313 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"}, string in object:register_types.CP_DMA_WORD1.fields.3
320 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"}, string in object:register_types.CP_DMA_WORD1_cik.fields.1
321 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, string in object:register_types.CP_DMA_WORD1_cik.fields.2
322 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"}, string in object:register_types.CP_DMA_WORD1_cik.fields.3
329 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"}, string in object:register_types.CP_DMA_WORD1_gfx9.fields.1
330 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, string in object:register_types.CP_DMA_WORD1_gfx9.fields.2
331 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"}, string in object:register_types.CP_DMA_WORD1_gfx9.fields.3
347 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, string in object:register_types.DMA_DATA_WORD0.fields.0
348 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"}, string in object:register_types.DMA_DATA_WORD0.fields.1
349 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"}, string in object:register_types.DMA_DATA_WORD0.fields.2
355 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, string in object:register_types.DMA_DATA_WORD0_cik.fields.0
357 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"}, string in object:register_types.DMA_DATA_WORD0_cik.fields.2
359 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"}, string in object:register_types.DMA_DATA_WORD0_cik.fields.4
365 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, string in object:register_types.DMA_DATA_WORD0_gfx9.fields.0
367 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"}, string in object:register_types.DMA_DATA_WORD0_gfx9.fields.2
369 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"}, string in object:register_types.DMA_DATA_WORD0_gfx9.fields.4
375 {"bits": [0, 1], "enum_ref": "GCR_GLI_INV", "name": "GLI_INV"}, string in object:register_types.GCR_CNTL.fields.0
376 {"bits": [2, 3], "enum_ref": "GCR_GL1_RANGE", "name": "GL1_RANGE"}, string in object:register_types.GCR_CNTL.fields.1
384 {"bits": [11, 12], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"}, string in object:register_types.GCR_CNTL.fields.9
388 {"bits": [16, 17], "enum_ref": "GCR_SEQ", "name": "SEQ"}, string in object:register_types.GCR_CNTL.fields.13
408 {"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"}, string in object:register_types.RELEASE_MEM_OP.fields.7
412 {"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"} string in object:register_types.RELEASE_MEM_OP.fields.11
[all...]
H A Dgfx7.json9066 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.0
9067 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.1
9068 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.2
9069 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.3
9070 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.4
9071 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.5
9094 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, string in object:register_types.CB_COLOR0_INFO.fields.0
9095 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, string in object:register_types.CB_COLOR0_INFO.fields.1
9097 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, string in object:register_types.CB_COLOR0_INFO.fields.3
9098 {"bits": [11, 12], "enum_ref" string in object:register_types.CB_COLOR0_INFO.fields.4
9106 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, string in object:register_types.CB_COLOR0_INFO.fields.12
9107 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, string in object:register_types.CB_COLOR0_INFO.fields.13
9131 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, string in object:register_types.CB_COLOR_CONTROL.fields.1
9132 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} string in object:register_types.CB_COLOR_CONTROL.fields.2
9161 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, string in object:register_types.CB_PERFCOUNTER_FILTER.fields.1
9165 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, string in object:register_types.CB_PERFCOUNTER_FILTER.fields.5
9244 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.COMPUTE_PGM_RSRC1.fields.3
9265 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.COMPUTE_PGM_RSRC2.fields.10
9746 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.0
9747 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.1
9748 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, string in object:register_types.CP_PERFMON_CNTL.fields.2
9877 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.4
9879 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.6
9880 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, string in object:register_types.DB_DEPTH_CONTROL.fields.7
9888 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, string in object:register_types.DB_DEPTH_INFO.fields.1
9889 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, string in object:register_types.DB_DEPTH_INFO.fields.2
9890 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, string in object:register_types.DB_DEPTH_INFO.fields.3
9891 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, string in object:register_types.DB_DEPTH_INFO.fields.4
9892 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, string in object:register_types.DB_DEPTH_INFO.fields.5
9893 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"} string in object:register_types.DB_DEPTH_INFO.fields.6
9982 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.0
9983 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.1
9984 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.2
9992 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.10
9997 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.15
10009 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.0
10018 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.9
10031 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, string in object:register_types.DB_SHADER_CONTROL.fields.3
10039 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"} string in object:register_types.DB_SHADER_CONTROL.fields.11
10044 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0
10052 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0
10081 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.0
10082 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, string in object:register_types.DB_STENCIL_CONTROL.fields.1
10083 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.2
10084 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.3
10085 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.4
10086 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} string in object:register_types.DB_STENCIL_CONTROL.fields.5
10091 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, string in object:register_types.DB_STENCIL_INFO.fields.0
10092 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.DB_STENCIL_INFO.fields.1
10105 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, string in object:register_types.DB_Z_INFO.fields.0
10107 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.DB_Z_INFO.fields.2
10130 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, string in object:register_types.GB_MACROTILE_MODE0.fields.0
10131 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, string in object:register_types.GB_MACROTILE_MODE0.fields.1
10132 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, string in object:register_types.GB_MACROTILE_MODE0.fields.2
10133 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"} string in object:register_types.GB_MACROTILE_MODE0.fields.3
10138 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, string in object:register_types.GB_TILE_MODE0.fields.0
10139 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, string in object:register_types.GB_TILE_MODE0.fields.1
10140 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.GB_TILE_MODE0.fields.2
10141 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, string in object:register_types.GB_TILE_MODE0.fields.3
10553 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} string in object:register_types.PA_SC_CLIPRECT_RULE.fields.0
10655 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.0
10656 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.1
10657 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.2
10658 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.3
10659 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.4
10660 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.5
10661 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.6
10662 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.7
10663 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.8
10664 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.9
10665 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.10
10666 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.11
10667 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.12
10668 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.13
10669 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG.fields.14
10674 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.0
10675 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.1
10676 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.2
10795 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, string in object:register_types.PA_SU_SC_MODE_CNTL.fields.3
10796 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ string in object:register_types.PA_SU_SC_MODE_CNTL.fields.4
10797 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE string in object:register_types.PA_SU_SC_MODE_CNTL.fields.5
10810 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, string in object:register_types.PA_SU_VTX_CNTL.fields.1
10811 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} string in object:register_types.PA_SU_VTX_CNTL.fields.2
10821 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.RLC_PERFMON_CNTL.fields.0
10887 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.2
10888 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.3
10889 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.4
10890 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.5
10958 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.0
10959 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.1
10960 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.2
10961 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.3
10962 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.4
10963 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.5
10964 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.6
10965 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_COL_FORMAT.fields.7
10978 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3
10993 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3
11007 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.3
11022 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3
11037 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.3
11054 {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.4
11063 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3
11073 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.5
11082 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.4
11092 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5
11106 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9
11124 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.0
11125 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.1
11126 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.2
11127 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_POS_FORMAT.fields.3
11137 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_Z_FORMAT.fields.0
11163 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.0
11164 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.1
11165 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.2
11166 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.3
11167 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.4
11168 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.5
11176 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} string in object:register_types.SQ_BUF_RSRC_WORD3.fields.13
11183 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.2
11184 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.3
11198 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.0
11199 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.1
11200 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.2
11201 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.3
11208 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} string in object:register_types.SQ_IMG_RSRC_WORD3.fields.10
11233 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.0
11234 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.1
11235 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.2
11237 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.4
11245 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"} string in object:register_types.SQ_IMG_SAMP_WORD0.fields.12
11260 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.2
11261 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.3
11262 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.4
11263 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.5
11273 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} string in object:register_types.SQ_IMG_SAMP_WORD3.fields.2
11289 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1
11290 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2
11291 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3
11292 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4
11293 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5
11452 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SQ_WAVE_MODE.fields.6
11497 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, string in object:register_types.SQ_WAVE_TRAPSTS.fields.0
11559 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.0
11560 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.1
11561 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.2
11562 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.3
11570 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.0
11571 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.1
11594 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, string in object:register_types.VGT_EVENT_INITIATOR.fields.0
11611 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, string in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0
11657 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, string in object:register_types.VGT_GS_MODE.fields.0
11659 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, string in object:register_types.VGT_GS_MODE.fields.2
11682 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0
11683 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1
11684 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2
11685 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3
11712 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP string in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.1
11717 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} string in object:register_types.VGT_INDEX_TYPE.fields.0
11761 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} string in object:register_types.VGT_PRIMITIVE_TYPE.fields.0
11771 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.0
11772 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.1
11773 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.2
11774 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.3
11775 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.4
11810 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, string in object:register_types.VGT_TF_PARAM.fields.0
11811 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, string in object:register_types.VGT_TF_PARAM.fields.1
11812 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, string in object:register_types.VGT_TF_PARAM.fields.2
11817 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"} string in object:register_types.VGT_TF_PARAM.fields.7
[all...]
H A Dgfx8.json9289 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.0
9290 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.1
9291 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.2
9292 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.3
9293 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.4
9294 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.5
9319 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"}, string in object:register_types.CB_COLOR0_DCC_CONTROL.fields.2
9320 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"}, string in object:register_types.CB_COLOR0_DCC_CONTROL.fields.3
9330 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, string in object:register_types.CB_COLOR0_INFO.fields.0
9331 {"bits": [2, 6], "enum_ref" string in object:register_types.CB_COLOR0_INFO.fields.1
9333 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, string in object:register_types.CB_COLOR0_INFO.fields.3
9334 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, string in object:register_types.CB_COLOR0_INFO.fields.4
9342 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, string in object:register_types.CB_COLOR0_INFO.fields.12
9343 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, string in object:register_types.CB_COLOR0_INFO.fields.13
9347 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"} string in object:register_types.CB_COLOR0_INFO.fields.17
9370 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, string in object:register_types.CB_COLOR_CONTROL.fields.1
9371 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} string in object:register_types.CB_COLOR_CONTROL.fields.2
9407 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, string in object:register_types.CB_PERFCOUNTER_FILTER.fields.1
9411 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, string in object:register_types.CB_PERFCOUNTER_FILTER.fields.5
9491 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.COMPUTE_PGM_RSRC1.fields.3
9512 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.COMPUTE_PGM_RSRC2.fields.10
9994 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} string in object:register_types.CP_INDEX_TYPE.fields.0
10025 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.0
10026 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.1
10027 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, string in object:register_types.CP_PERFMON_CNTL.fields.2
10186 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.4
10188 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.6
10189 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, string in object:register_types.DB_DEPTH_CONTROL.fields.7
10197 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, string in object:register_types.DB_DEPTH_INFO.fields.1
10198 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, string in object:register_types.DB_DEPTH_INFO.fields.2
10199 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, string in object:register_types.DB_DEPTH_INFO.fields.3
10200 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, string in object:register_types.DB_DEPTH_INFO.fields.4
10201 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, string in object:register_types.DB_DEPTH_INFO.fields.5
10202 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"} string in object:register_types.DB_DEPTH_INFO.fields.6
10293 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.0
10294 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.1
10295 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.2
10303 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.10
10308 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.15
10320 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.0
10329 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.9
10342 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, string in object:register_types.DB_SHADER_CONTROL.fields.3
10350 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"} string in object:register_types.DB_SHADER_CONTROL.fields.11
10355 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0
10363 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0
10392 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.0
10393 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, string in object:register_types.DB_STENCIL_CONTROL.fields.1
10394 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.2
10395 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.3
10396 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.4
10397 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} string in object:register_types.DB_STENCIL_CONTROL.fields.5
10402 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, string in object:register_types.DB_STENCIL_INFO.fields.0
10403 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.DB_STENCIL_INFO.fields.1
10417 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, string in object:register_types.DB_Z_INFO.fields.0
10419 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.DB_Z_INFO.fields.2
10444 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, string in object:register_types.GB_MACROTILE_MODE0.fields.0
10445 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, string in object:register_types.GB_MACROTILE_MODE0.fields.1
10446 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, string in object:register_types.GB_MACROTILE_MODE0.fields.2
10447 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"} string in object:register_types.GB_MACROTILE_MODE0.fields.3
10452 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, string in object:register_types.GB_TILE_MODE0.fields.0
10453 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, string in object:register_types.GB_TILE_MODE0.fields.1
10454 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.GB_TILE_MODE0.fields.2
10455 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, string in object:register_types.GB_TILE_MODE0.fields.3
10870 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} string in object:register_types.PA_SC_CLIPRECT_RULE.fields.0
10972 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.0
10973 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.1
10974 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.2
10975 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.3
10976 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.4
10977 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.5
10978 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.6
10979 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.7
10980 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.8
10981 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.9
10982 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.10
10983 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.11
10984 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.12
10985 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.13
10986 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG.fields.14
10991 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.0
10992 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.1
10993 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.2
11112 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, string in object:register_types.PA_SU_SC_MODE_CNTL.fields.3
11113 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ string in object:register_types.PA_SU_SC_MODE_CNTL.fields.4
11114 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE string in object:register_types.PA_SU_SC_MODE_CNTL.fields.5
11127 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, string in object:register_types.PA_SU_VTX_CNTL.fields.1
11128 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} string in object:register_types.PA_SU_VTX_CNTL.fields.2
11143 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.RLC_PERFMON_CNTL.fields.0
11209 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.2
11210 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.3
11211 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.4
11212 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.5
11291 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.0
11292 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.1
11293 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.2
11294 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.3
11295 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.4
11296 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.5
11297 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.6
11298 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_COL_FORMAT.fields.7
11311 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3
11326 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3
11340 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.3
11355 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3
11370 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.3
11387 {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.4
11396 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3
11406 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.5
11415 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.4
11425 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5
11439 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9
11467 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.0
11468 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.1
11469 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.2
11470 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_POS_FORMAT.fields.3
11480 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_Z_FORMAT.fields.0
11515 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.0
11516 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.1
11517 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.2
11518 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.3
11519 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.4
11520 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.5
11528 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} string in object:register_types.SQ_BUF_RSRC_WORD3.fields.13
11535 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.2
11536 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.3
11550 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.0
11551 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.1
11552 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.2
11553 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.3
11560 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} string in object:register_types.SQ_IMG_RSRC_WORD3.fields.10
11589 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.0
11590 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.1
11591 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.2
11593 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.4
11601 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.12
11617 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.2
11618 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.3
11619 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.4
11620 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.5
11631 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} string in object:register_types.SQ_IMG_SAMP_WORD3.fields.2
11647 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1
11648 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2
11649 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3
11650 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4
11651 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5
11814 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SQ_WAVE_MODE.fields.6
11859 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, string in object:register_types.SQ_WAVE_TRAPSTS.fields.0
11922 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.0
11923 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.1
11924 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.2
11925 {"bits": [6, 6], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.3
11933 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.0
11934 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.1
11957 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, string in object:register_types.VGT_EVENT_INITIATOR.fields.0
11974 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, string in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0
12020 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, string in object:register_types.VGT_GS_MODE.fields.0
12022 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, string in object:register_types.VGT_GS_MODE.fields.2
12045 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0
12046 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1
12047 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2
12048 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3
12075 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP string in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.1
12119 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} string in object:register_types.VGT_PRIMITIVE_TYPE.fields.0
12129 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.0
12130 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.1
12131 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.2
12132 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.3
12133 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.4
12179 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, string in object:register_types.VGT_TF_PARAM.fields.0
12180 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, string in object:register_types.VGT_TF_PARAM.fields.1
12181 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, string in object:register_types.VGT_TF_PARAM.fields.2
12186 {"bits": [15, 15], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, string in object:register_types.VGT_TF_PARAM.fields.7
12187 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"}, string in object:register_types.VGT_TF_PARAM.fields.8
[all...]
H A Dgfx81.json9394 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.0
9395 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.1
9396 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.2
9397 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.3
9398 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.4
9399 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.5
9424 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"}, string in object:register_types.CB_COLOR0_DCC_CONTROL.fields.2
9425 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"}, string in object:register_types.CB_COLOR0_DCC_CONTROL.fields.3
9435 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, string in object:register_types.CB_COLOR0_INFO.fields.0
9436 {"bits": [2, 6], "enum_ref" string in object:register_types.CB_COLOR0_INFO.fields.1
9438 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, string in object:register_types.CB_COLOR0_INFO.fields.3
9439 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, string in object:register_types.CB_COLOR0_INFO.fields.4
9447 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, string in object:register_types.CB_COLOR0_INFO.fields.12
9448 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, string in object:register_types.CB_COLOR0_INFO.fields.13
9452 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"} string in object:register_types.CB_COLOR0_INFO.fields.17
9476 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, string in object:register_types.CB_COLOR_CONTROL.fields.2
9477 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} string in object:register_types.CB_COLOR_CONTROL.fields.3
9513 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, string in object:register_types.CB_PERFCOUNTER_FILTER.fields.1
9517 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, string in object:register_types.CB_PERFCOUNTER_FILTER.fields.5
9597 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.COMPUTE_PGM_RSRC1.fields.3
9618 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.COMPUTE_PGM_RSRC2.fields.10
10100 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} string in object:register_types.CP_INDEX_TYPE.fields.0
10131 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.0
10132 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.1
10133 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, string in object:register_types.CP_PERFMON_CNTL.fields.2
10292 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.4
10294 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.6
10295 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, string in object:register_types.DB_DEPTH_CONTROL.fields.7
10303 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, string in object:register_types.DB_DEPTH_INFO.fields.1
10304 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, string in object:register_types.DB_DEPTH_INFO.fields.2
10305 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, string in object:register_types.DB_DEPTH_INFO.fields.3
10306 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, string in object:register_types.DB_DEPTH_INFO.fields.4
10307 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, string in object:register_types.DB_DEPTH_INFO.fields.5
10308 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"} string in object:register_types.DB_DEPTH_INFO.fields.6
10399 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.0
10400 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.1
10401 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.2
10409 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.10
10414 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.15
10426 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.0
10435 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.9
10448 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, string in object:register_types.DB_SHADER_CONTROL.fields.3
10456 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"}, string in object:register_types.DB_SHADER_CONTROL.fields.11
10462 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0
10470 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0
10499 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.0
10500 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, string in object:register_types.DB_STENCIL_CONTROL.fields.1
10501 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.2
10502 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.3
10503 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.4
10504 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} string in object:register_types.DB_STENCIL_CONTROL.fields.5
10509 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, string in object:register_types.DB_STENCIL_INFO.fields.0
10510 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.DB_STENCIL_INFO.fields.1
10524 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, string in object:register_types.DB_Z_INFO.fields.0
10526 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.DB_Z_INFO.fields.2
10551 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, string in object:register_types.GB_MACROTILE_MODE0.fields.0
10552 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, string in object:register_types.GB_MACROTILE_MODE0.fields.1
10553 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, string in object:register_types.GB_MACROTILE_MODE0.fields.2
10554 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"} string in object:register_types.GB_MACROTILE_MODE0.fields.3
10559 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, string in object:register_types.GB_TILE_MODE0.fields.0
10560 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, string in object:register_types.GB_TILE_MODE0.fields.1
10561 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.GB_TILE_MODE0.fields.2
10562 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, string in object:register_types.GB_TILE_MODE0.fields.3
10977 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} string in object:register_types.PA_SC_CLIPRECT_RULE.fields.0
11079 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.0
11080 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.1
11081 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.2
11082 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.3
11083 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.4
11084 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.5
11085 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.6
11086 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.7
11087 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.8
11088 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.9
11089 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.10
11090 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.11
11091 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.12
11092 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.13
11093 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG.fields.14
11098 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.0
11099 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.1
11100 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.2
11224 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, string in object:register_types.PA_SU_SC_MODE_CNTL.fields.3
11225 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ string in object:register_types.PA_SU_SC_MODE_CNTL.fields.4
11226 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE string in object:register_types.PA_SU_SC_MODE_CNTL.fields.5
11239 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, string in object:register_types.PA_SU_VTX_CNTL.fields.1
11240 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} string in object:register_types.PA_SU_VTX_CNTL.fields.2
11255 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.RLC_PERFMON_CNTL.fields.0
11321 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.2
11322 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.3
11323 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.4
11324 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.5
11403 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.0
11404 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.1
11405 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.2
11406 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.3
11407 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.4
11408 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.5
11409 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.6
11410 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_COL_FORMAT.fields.7
11423 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3
11438 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3
11452 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.3
11467 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3
11482 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.3
11499 {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.4
11508 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3
11518 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.5
11527 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.4
11537 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5
11551 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9
11579 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.0
11580 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.1
11581 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.2
11582 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_POS_FORMAT.fields.3
11592 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_Z_FORMAT.fields.0
11627 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.0
11628 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.1
11629 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.2
11630 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.3
11631 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.4
11632 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.5
11640 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} string in object:register_types.SQ_BUF_RSRC_WORD3.fields.13
11647 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.2
11648 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.3
11662 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.0
11663 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.1
11664 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.2
11665 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.3
11672 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} string in object:register_types.SQ_IMG_RSRC_WORD3.fields.10
11701 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.0
11702 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.1
11703 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.2
11705 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.4
11713 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.12
11729 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.2
11730 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.3
11731 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.4
11732 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.5
11743 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} string in object:register_types.SQ_IMG_SAMP_WORD3.fields.2
11759 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1
11760 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2
11761 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3
11762 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4
11763 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5
11926 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SQ_WAVE_MODE.fields.6
11971 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, string in object:register_types.SQ_WAVE_TRAPSTS.fields.0
12000 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"}, string in object:register_types.SX_BLEND_OPT_EPSILON.fields.0
12012 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.0
12013 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.1
12014 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.2
12015 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.3
12016 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.4
12017 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"} string in object:register_types.SX_MRT0_BLEND_OPT.fields.5
12035 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.0
12036 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.1
12037 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.2
12038 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.3
12039 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.4
12040 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.5
12041 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.6
12042 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"} string in object:register_types.SX_PS_DOWNCONVERT.fields.7
12089 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.0
12090 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.1
12091 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.2
12092 {"bits": [6, 6], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.3
12100 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.0
12101 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.1
12124 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, string in object:register_types.VGT_EVENT_INITIATOR.fields.0
12141 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, string in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0
12187 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, string in object:register_types.VGT_GS_MODE.fields.0
12189 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, string in object:register_types.VGT_GS_MODE.fields.2
12212 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0
12213 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1
12214 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2
12215 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3
12242 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP string in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.1
12286 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} string in object:register_types.VGT_PRIMITIVE_TYPE.fields.0
12296 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.0
12297 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.1
12298 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.2
12299 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.3
12300 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.4
12347 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, string in object:register_types.VGT_TF_PARAM.fields.0
12348 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, string in object:register_types.VGT_TF_PARAM.fields.1
12349 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, string in object:register_types.VGT_TF_PARAM.fields.2
12354 {"bits": [15, 15], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, string in object:register_types.VGT_TF_PARAM.fields.7
12355 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"}, string in object:register_types.VGT_TF_PARAM.fields.8
[all...]
H A Dgfx6.json7648 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.0
7649 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.1
7650 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.2
7651 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.3
7652 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.4
7653 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.5
7681 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, string in object:register_types.CB_COLOR0_INFO.fields.0
7682 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, string in object:register_types.CB_COLOR0_INFO.fields.1
7684 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, string in object:register_types.CB_COLOR0_INFO.fields.3
7685 {"bits": [11, 12], "enum_ref" string in object:register_types.CB_COLOR0_INFO.fields.4
7693 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, string in object:register_types.CB_COLOR0_INFO.fields.12
7694 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, string in object:register_types.CB_COLOR0_INFO.fields.13
7713 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, string in object:register_types.CB_COLOR_CONTROL.fields.1
7714 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} string in object:register_types.CB_COLOR_CONTROL.fields.2
7854 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.COMPUTE_PGM_RSRC1.fields.3
7875 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.COMPUTE_PGM_RSRC2.fields.10
8249 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.0
8250 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.1
8251 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, string in object:register_types.CP_PERFMON_CNTL.fields.2
8564 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.4
8566 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.6
8567 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, string in object:register_types.DB_DEPTH_CONTROL.fields.7
8575 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, string in object:register_types.DB_DEPTH_INFO.fields.1
8576 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, string in object:register_types.DB_DEPTH_INFO.fields.2
8577 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, string in object:register_types.DB_DEPTH_INFO.fields.3
8578 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, string in object:register_types.DB_DEPTH_INFO.fields.4
8579 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, string in object:register_types.DB_DEPTH_INFO.fields.5
8580 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"} string in object:register_types.DB_DEPTH_INFO.fields.6
8652 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.0
8653 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.1
8654 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.2
8662 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.10
8667 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.15
8679 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.0
8688 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.9
8701 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, string in object:register_types.DB_SHADER_CONTROL.fields.3
8709 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"} string in object:register_types.DB_SHADER_CONTROL.fields.11
8714 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0
8722 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0
8751 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.0
8752 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, string in object:register_types.DB_STENCIL_CONTROL.fields.1
8753 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.2
8754 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.3
8755 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.4
8756 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} string in object:register_types.DB_STENCIL_CONTROL.fields.5
8761 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, string in object:register_types.DB_STENCIL_INFO.fields.0
8762 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.DB_STENCIL_INFO.fields.1
8770 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, string in object:register_types.DB_Z_INFO.fields.0
8772 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.DB_Z_INFO.fields.2
8800 {"bits": [0, 1], "enum_ref": "GB_TILE_MODE0__MICRO_TILE_MODE", "name": "MICRO_TILE_MODE"}, string in object:register_types.GB_TILE_MODE0.fields.0
8801 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, string in object:register_types.GB_TILE_MODE0.fields.1
8802 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, string in object:register_types.GB_TILE_MODE0.fields.2
8803 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.GB_TILE_MODE0.fields.3
8804 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, string in object:register_types.GB_TILE_MODE0.fields.4
8810 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, string in object:register_types.GB_TILE_MODE10.fields.0
8811 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, string in object:register_types.GB_TILE_MODE10.fields.1
8812 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.GB_TILE_MODE10.fields.2
8813 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, string in object:register_types.GB_TILE_MODE10.fields.3
9281 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} string in object:register_types.PA_SC_CLIPRECT_RULE.fields.0
9436 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.0
9437 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.1
9438 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.2
9439 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.3
9440 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.4
9441 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.5
9442 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.6
9443 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.7
9444 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.8
9445 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.9
9446 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.10
9447 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.11
9448 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.12
9449 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.13
9450 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG.fields.14
9561 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, string in object:register_types.PA_SU_SC_MODE_CNTL.fields.3
9562 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ string in object:register_types.PA_SU_SC_MODE_CNTL.fields.4
9563 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE string in object:register_types.PA_SU_SC_MODE_CNTL.fields.5
9576 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, string in object:register_types.PA_SU_VTX_CNTL.fields.1
9577 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} string in object:register_types.PA_SU_VTX_CNTL.fields.2
9611 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.2
9612 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.3
9613 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.4
9614 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.5
9665 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.0
9666 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.1
9667 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.2
9668 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.3
9669 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.4
9670 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.5
9671 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.6
9672 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_COL_FORMAT.fields.7
9685 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.3
9701 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3
9716 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3
9730 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.3
9745 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3
9761 {"bits": [8, 14], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_ES.fields.4
9770 {"bits": [7, 13], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3
9780 {"bits": [9, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.5
9789 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_LS.fields.4
9799 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5
9813 {"bits": [13, 19], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9
9818 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.0
9819 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.1
9820 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.2
9821 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_POS_FORMAT.fields.3
9826 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_Z_FORMAT.fields.0
9879 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.0
9880 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.1
9881 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.2
9882 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.3
9883 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.4
9884 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.5
9892 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} string in object:register_types.SQ_BUF_RSRC_WORD3.fields.13
9943 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.2
9944 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.3
9958 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.0
9959 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.1
9960 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.2
9961 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.3
9968 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} string in object:register_types.SQ_IMG_RSRC_WORD3.fields.10
9993 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.0
9994 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.1
9995 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.2
9997 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.4
10005 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"} string in object:register_types.SQ_IMG_SAMP_WORD0.fields.12
10020 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.2
10021 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.3
10022 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.4
10023 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.5
10033 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} string in object:register_types.SQ_IMG_SAMP_WORD3.fields.2
10082 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1
10083 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2
10084 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3
10085 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4
10086 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5
10267 {"bits": [12, 18], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SQ_WAVE_MODE.fields.6
10312 {"bits": [0, 6], "enum_ref": "EXCP_EN", "name": "EXCP"}, string in object:register_types.SQ_WAVE_TRAPSTS.fields.0
10361 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.0
10362 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.1
10363 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.2
10364 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.3
10377 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.0
10378 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.1
10406 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, string in object:register_types.VGT_EVENT_INITIATOR.fields.0
10431 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, string in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0
10477 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, string in object:register_types.VGT_GS_MODE.fields.0
10479 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, string in object:register_types.VGT_GS_MODE.fields.2
10496 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0
10497 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1
10498 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2
10499 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3
10531 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP string in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.1
10536 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} string in object:register_types.VGT_INDEX_TYPE.fields.0
10585 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} string in object:register_types.VGT_PRIMITIVE_TYPE.fields.0
10595 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.0
10596 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.1
10597 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.2
10598 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.3
10599 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.4
10641 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, string in object:register_types.VGT_TF_PARAM.fields.0
10642 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, string in object:register_types.VGT_TF_PARAM.fields.1
10643 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, string in object:register_types.VGT_TF_PARAM.fields.2
10648 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"} string in object:register_types.VGT_TF_PARAM.fields.7
[all...]
H A Dgfx9.json10327 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.0
10328 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.1
10329 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.2
10330 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.3
10331 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.4
10332 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.5
10368 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"}, string in object:register_types.CB_COLOR0_DCC_CONTROL.fields.2
10369 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"}, string in object:register_types.CB_COLOR0_DCC_CONTROL.fields.3
10381 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, string in object:register_types.CB_COLOR0_INFO.fields.0
10382 {"bits": [2, 6], "enum_ref" string in object:register_types.CB_COLOR0_INFO.fields.1
10383 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, string in object:register_types.CB_COLOR0_INFO.fields.2
10384 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, string in object:register_types.CB_COLOR0_INFO.fields.3
10391 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, string in object:register_types.CB_COLOR0_INFO.fields.10
10392 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, string in object:register_types.CB_COLOR0_INFO.fields.11
10396 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"} string in object:register_types.CB_COLOR0_INFO.fields.15
10410 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, string in object:register_types.CB_COLOR_CONTROL.fields.2
10411 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} string in object:register_types.CB_COLOR_CONTROL.fields.3
10453 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, string in object:register_types.CB_PERFCOUNTER_FILTER.fields.1
10457 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, string in object:register_types.CB_PERFCOUNTER_FILTER.fields.5
10540 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.COMPUTE_PGM_RSRC1.fields.3
10562 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.COMPUTE_PGM_RSRC2.fields.10
11061 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} string in object:register_types.CP_INDEX_TYPE.fields.0
11111 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.0
11112 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.1
11113 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, string in object:register_types.CP_PERFMON_CNTL.fields.2
11276 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.4
11278 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.6
11279 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, string in object:register_types.DB_DEPTH_CONTROL.fields.7
11301 {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"}, string in object:register_types.DB_DFSM_CONTROL.fields.0
11368 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.0
11369 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.1
11370 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.2
11378 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.10
11383 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.15
11395 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.0
11404 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.9
11418 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, string in object:register_types.DB_SHADER_CONTROL.fields.3
11426 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"}, string in object:register_types.DB_SHADER_CONTROL.fields.11
11435 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0
11443 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0
11472 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.0
11473 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, string in object:register_types.DB_STENCIL_CONTROL.fields.1
11474 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.2
11475 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.3
11476 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.4
11477 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} string in object:register_types.DB_STENCIL_CONTROL.fields.5
11482 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, string in object:register_types.DB_STENCIL_INFO.fields.0
11485 {"bits": [13, 14], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, string in object:register_types.DB_STENCIL_INFO.fields.3
11494 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, string in object:register_types.DB_Z_INFO.fields.0
11498 {"bits": [13, 14], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, string in object:register_types.DB_Z_INFO.fields.4
11520 {"bits": [12, 14], "enum_ref": "NumBanks", "name": "NUM_BANKS"}, string in object:register_types.GB_ADDR_CONFIG.fields.4
11533 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, string in object:register_types.GB_MACROTILE_MODE0.fields.0
11534 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, string in object:register_types.GB_MACROTILE_MODE0.fields.1
11535 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, string in object:register_types.GB_MACROTILE_MODE0.fields.2
11536 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"} string in object:register_types.GB_MACROTILE_MODE0.fields.3
11541 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, string in object:register_types.GB_TILE_MODE0.fields.0
11542 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, string in object:register_types.GB_TILE_MODE0.fields.1
11543 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.GB_TILE_MODE0.fields.2
11544 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, string in object:register_types.GB_TILE_MODE0.fields.3
11906 {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"} string in object:register_types.PA_SC_AA_CONFIG.fields.5
11971 {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"}, string in object:register_types.PA_SC_BINNER_CNTL_0.fields.0
12022 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} string in object:register_types.PA_SC_CLIPRECT_RULE.fields.0
12161 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.0
12162 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.1
12163 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.2
12164 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.3
12165 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.4
12166 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.5
12167 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.6
12168 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.7
12169 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.8
12170 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.9
12171 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.10
12172 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.11
12173 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.12
12174 {"bits": [26, 28], "enum_ref": "SeXsel", "name": "SE_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.13
12175 {"bits": [29, 31], "enum_ref": "SeYsel", "name": "SE_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG.fields.14
12180 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.0
12181 {"bits": [2, 4], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.1
12182 {"bits": [5, 7], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.2
12343 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, string in object:register_types.PA_SU_SC_MODE_CNTL.fields.3
12344 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ string in object:register_types.PA_SU_SC_MODE_CNTL.fields.4
12345 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE string in object:register_types.PA_SU_SC_MODE_CNTL.fields.5
12370 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, string in object:register_types.PA_SU_VTX_CNTL.fields.1
12371 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} string in object:register_types.PA_SU_VTX_CNTL.fields.2
12413 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.RLC_PERFMON_CNTL.fields.0
12523 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.2
12524 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.3
12525 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.4
12526 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.5
12607 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.0
12608 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.1
12609 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.2
12610 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.3
12611 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.4
12612 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.5
12613 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.6
12614 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_COL_FORMAT.fields.7
12632 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3
12648 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3
12663 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3
12678 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.3
12694 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3
12707 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.3
12720 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.3
12733 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5
12751 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9
12787 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.0
12788 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.1
12789 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.2
12790 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_POS_FORMAT.fields.3
12795 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_Z_FORMAT.fields.0
12838 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.0
12839 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.1
12840 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.2
12841 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.3
12842 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.4
12843 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, string in object:register_types.SQ_BUF_RSRC_WORD3.fields.5
12849 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} string in object:register_types.SQ_BUF_RSRC_WORD3.fields.11
12856 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.2
12857 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT_STENCIL", "name": "DATA_FORMAT_STENCIL"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.3
12858 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.4
12859 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT_FMASK", "name": "NUM_FORMAT_FMASK"}, string in object:register_types.SQ_IMG_RSRC_WORD1.fields.5
12873 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.0
12874 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.1
12875 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.2
12876 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, string in object:register_types.SQ_IMG_RSRC_WORD3.fields.3
12880 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} string in object:register_types.SQ_IMG_RSRC_WORD3.fields.7
12887 {"bits": [29, 31], "enum_ref": "SQ_IMG_RSRC_WORD4__BC_SWIZZLE", "name": "BC_SWIZZLE"} string in object:register_types.SQ_IMG_RSRC_WORD4.fields.2
12915 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.0
12916 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.1
12917 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.2
12919 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.4
12927 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"}, string in object:register_types.SQ_IMG_SAMP_WORD0.fields.12
12943 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.2
12944 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.3
12945 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.4
12946 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, string in object:register_types.SQ_IMG_SAMP_WORD2.fields.5
12957 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} string in object:register_types.SQ_IMG_SAMP_WORD3.fields.2
12973 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1
12974 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2
12975 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3
12976 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4
12977 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5
13143 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SQ_WAVE_MODE.fields.6
13187 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, string in object:register_types.SQ_WAVE_TRAPSTS.fields.0
13219 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"}, string in object:register_types.SX_BLEND_OPT_EPSILON.fields.0
13231 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.0
13232 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.1
13233 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.2
13234 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.3
13235 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.4
13236 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"} string in object:register_types.SX_MRT0_BLEND_OPT.fields.5
13241 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.0
13242 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.1
13243 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.2
13244 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.3
13245 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.4
13246 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.5
13247 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.6
13248 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"} string in object:register_types.SX_PS_DOWNCONVERT.fields.7
13295 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.0
13296 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.1
13297 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.2
13298 {"bits": [6, 6], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.3
13306 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.0
13307 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.1
13341 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, string in object:register_types.VGT_EVENT_INITIATOR.fields.0
13358 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, string in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0
13409 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, string in object:register_types.VGT_GS_MODE.fields.0
13411 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, string in object:register_types.VGT_GS_MODE.fields.2
13435 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0
13436 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1
13437 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2
13438 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3
13465 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP string in object:register_types.VGT_HS_OFFCHIP_PARAM.fields.1
13470 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, string in object:register_types.VGT_INDEX_TYPE.fields.0
13511 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} string in object:register_types.VGT_PRIMITIVE_TYPE.fields.0
13521 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.0
13522 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.1
13523 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.2
13524 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.3
13525 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.4
13577 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, string in object:register_types.VGT_TF_PARAM.fields.0
13578 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, string in object:register_types.VGT_TF_PARAM.fields.1
13579 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, string in object:register_types.VGT_TF_PARAM.fields.2
13583 {"bits": [15, 15], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, string in object:register_types.VGT_TF_PARAM.fields.6
13584 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"} string in object:register_types.VGT_TF_PARAM.fields.7
[all...]
H A Dgfx10.json11592 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.0
11593 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.1
11594 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.2
11595 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.3
11596 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.4
11597 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.5
11648 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"}, string in object:register_types.CB_COLOR0_DCC_CONTROL.fields.2
11649 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"}, string in object:register_types.CB_COLOR0_DCC_CONTROL.fields.3
11662 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, string in object:register_types.CB_COLOR0_INFO.fields.0
11663 {"bits": [2, 6], "enum_ref" string in object:register_types.CB_COLOR0_INFO.fields.1
11665 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, string in object:register_types.CB_COLOR0_INFO.fields.3
11666 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, string in object:register_types.CB_COLOR0_INFO.fields.4
11674 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, string in object:register_types.CB_COLOR0_INFO.fields.12
11675 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, string in object:register_types.CB_COLOR0_INFO.fields.13
11679 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"}, string in object:register_types.CB_COLOR0_INFO.fields.17
11705 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, string in object:register_types.CB_COLOR_CONTROL.fields.2
11706 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} string in object:register_types.CB_COLOR_CONTROL.fields.3
11755 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, string in object:register_types.CB_PERFCOUNTER_FILTER.fields.1
11759 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, string in object:register_types.CB_PERFCOUNTER_FILTER.fields.5
11770 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.0
11771 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.1
11772 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.2
11773 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.3
11774 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.4
11775 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.5
11776 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.6
11777 {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.7
11869 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.COMPUTE_PGM_RSRC1.fields.3
11892 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.COMPUTE_PGM_RSRC2.fields.10
12477 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} string in object:register_types.CP_INDEX_TYPE.fields.0
12527 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.0
12528 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.1
12529 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, string in object:register_types.CP_PERFMON_CNTL.fields.2
12695 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.4
12697 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.6
12698 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, string in object:register_types.DB_DEPTH_CONTROL.fields.7
12722 {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"}, string in object:register_types.DB_DFSM_CONTROL.fields.0
12785 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.0
12786 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.1
12787 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.2
12795 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.10
12800 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.15
12812 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.0
12821 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.9
12855 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.0
12856 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.1
12857 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.2
12858 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.3
12859 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.4
12860 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.5
12861 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.6
12871 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, string in object:register_types.DB_SHADER_CONTROL.fields.3
12879 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"}, string in object:register_types.DB_SHADER_CONTROL.fields.11
12889 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0
12897 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0
12926 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.0
12927 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, string in object:register_types.DB_STENCIL_CONTROL.fields.1
12928 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.2
12929 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.3
12930 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.4
12931 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} string in object:register_types.DB_STENCIL_CONTROL.fields.5
12936 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, string in object:register_types.DB_STENCIL_INFO.fields.0
12938 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, string in object:register_types.DB_STENCIL_INFO.fields.2
12949 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, string in object:register_types.DB_Z_INFO.fields.0
12952 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, string in object:register_types.DB_Z_INFO.fields.3
12981 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, string in object:register_types.GB_MACROTILE_MODE0.fields.0
12982 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, string in object:register_types.GB_MACROTILE_MODE0.fields.1
12983 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, string in object:register_types.GB_MACROTILE_MODE0.fields.2
12984 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"} string in object:register_types.GB_MACROTILE_MODE0.fields.3
12989 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, string in object:register_types.GB_TILE_MODE0.fields.0
12990 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, string in object:register_types.GB_TILE_MODE0.fields.1
12991 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, string in object:register_types.GB_TILE_MODE0.fields.2
12992 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, string in object:register_types.GB_TILE_MODE0.fields.3
13484 {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"} string in object:register_types.PA_SC_AA_CONFIG.fields.5
13549 {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"}, string in object:register_types.PA_SC_BINNER_CNTL_0.fields.0
13552 {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"}, string in object:register_types.PA_SC_BINNER_CNTL_0.fields.3
13553 {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"}, string in object:register_types.PA_SC_BINNER_CNTL_0.fields.4
13560 {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"} string in object:register_types.PA_SC_BINNER_CNTL_0.fields.11
13601 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} string in object:register_types.PA_SC_CLIPRECT_RULE.fields.0
13616 {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE" string in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.10
13743 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.0
13744 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.1
13745 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.2
13746 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.3
13747 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.4
13748 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.5
13749 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.6
13750 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.7
13751 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.8
13752 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.9
13753 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.10
13754 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.11
13755 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.12
13756 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.13
13757 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG.fields.14
13762 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.0
13763 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.1
13764 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.2
13939 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, string in object:register_types.PA_SU_SC_MODE_CNTL.fields.3
13940 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ string in object:register_types.PA_SU_SC_MODE_CNTL.fields.4
13941 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE string in object:register_types.PA_SU_SC_MODE_CNTL.fields.5
13968 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, string in object:register_types.PA_SU_VTX_CNTL.fields.1
13969 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} string in object:register_types.PA_SU_VTX_CNTL.fields.2
14011 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.RLC_PERFMON_CNTL.fields.0
14247 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.2
14248 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.3
14249 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.4
14250 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.5
14327 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.0
14328 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.1
14329 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.2
14330 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.3
14331 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.4
14332 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.5
14333 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.6
14334 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_COL_FORMAT.fields.7
14339 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_IDX_FORMAT.fields.0
14357 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_ES.fields.3
14371 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3
14388 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3
14404 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_LS.fields.3
14417 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3
14432 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.3
14449 {"bits": [8, 16], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_ES_VS.fields.4
14458 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3
14471 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.3
14486 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.5
14498 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.SPI_SHADER_PGM_RSRC2_LS_VS.fields.4
14508 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5
14526 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9
14569 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.0
14570 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.1
14571 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.2
14572 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.3
14573 {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_POS_FORMAT.fields.4
14604 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_Z_FORMAT.fields.0
14642 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1
14643 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2
14644 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3
14645 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4
14646 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5
14704 {"bits": [0, 11], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"}, string in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.0
14705 {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"}, string in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.1
14813 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SQ_WAVE_MODE.fields.5
14862 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, string in object:register_types.SQ_WAVE_TRAPSTS.fields.0
14905 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"}, string in object:register_types.SX_BLEND_OPT_EPSILON.fields.0
14917 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.0
14918 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.1
14919 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.2
14920 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.3
14921 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.4
14922 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"} string in object:register_types.SX_MRT0_BLEND_OPT.fields.5
14940 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.0
14941 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.1
14942 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.2
14943 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.3
14944 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.4
14945 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.5
14946 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.6
14947 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"} string in object:register_types.SX_PS_DOWNCONVERT.fields.7
14999 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.0
15000 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.1
15001 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.2
15002 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.3
15011 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.0
15012 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.1
15047 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, string in object:register_types.VGT_EVENT_INITIATOR.fields.0
15064 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, string in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0
15111 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, string in object:register_types.VGT_GS_MODE.fields.0
15113 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, string in object:register_types.VGT_GS_MODE.fields.2
15137 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0
15138 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1
15139 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2
15140 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3
15167 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP string in object:register_types.VGT_HS_OFFCHIP_PARAM_UMD.fields.1
15202 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} string in object:register_types.VGT_PRIMITIVE_TYPE.fields.0
15212 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.0
15213 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.1
15214 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.2
15215 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.3
15216 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.4
15274 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, string in object:register_types.VGT_TF_PARAM.fields.0
15275 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, string in object:register_types.VGT_TF_PARAM.fields.1
15276 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, string in object:register_types.VGT_TF_PARAM.fields.2
15281 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, string in object:register_types.VGT_TF_PARAM.fields.7
15282 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"}, string in object:register_types.VGT_TF_PARAM.fields.8
15283 {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"}, string in object:register_types.VGT_TF_PARAM.fields.9
15284 {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"}, string in object:register_types.VGT_TF_PARAM.fields.10
[all...]
H A Dgfx103.json11474 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.0
11475 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.1
11476 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.2
11477 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.3
11478 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, string in object:register_types.CB_BLEND0_CONTROL.fields.4
11479 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, string in object:register_types.CB_BLEND0_CONTROL.fields.5
11531 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"}, string in object:register_types.CB_COLOR0_DCC_CONTROL.fields.2
11532 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"}, string in object:register_types.CB_COLOR0_DCC_CONTROL.fields.3
11547 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, string in object:register_types.CB_COLOR0_INFO.fields.0
11548 {"bits": [2, 6], "enum_ref" string in object:register_types.CB_COLOR0_INFO.fields.1
11550 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, string in object:register_types.CB_COLOR0_INFO.fields.3
11551 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, string in object:register_types.CB_COLOR0_INFO.fields.4
11559 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, string in object:register_types.CB_COLOR0_INFO.fields.12
11560 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, string in object:register_types.CB_COLOR0_INFO.fields.13
11564 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"}, string in object:register_types.CB_COLOR0_INFO.fields.17
11591 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, string in object:register_types.CB_COLOR_CONTROL.fields.3
11592 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} string in object:register_types.CB_COLOR_CONTROL.fields.4
11641 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, string in object:register_types.CB_PERFCOUNTER_FILTER.fields.1
11645 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, string in object:register_types.CB_PERFCOUNTER_FILTER.fields.5
11656 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "CMASK_WR_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.0
11657 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "FMASK_WR_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.1
11658 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.2
11659 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.3
11660 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "CMASK_RD_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.4
11661 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "FMASK_RD_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.5
11662 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.6
11663 {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"}, string in object:register_types.CB_RMI_GL2_CACHE_CONTROL.fields.7
11759 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.COMPUTE_PGM_RSRC1.fields.3
11782 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} string in object:register_types.COMPUTE_PGM_RSRC2.fields.10
12359 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} string in object:register_types.CP_INDEX_TYPE.fields.0
12409 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.0
12410 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, string in object:register_types.CP_PERFMON_CNTL.fields.1
12411 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, string in object:register_types.CP_PERFMON_CNTL.fields.2
12572 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.4
12574 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, string in object:register_types.DB_DEPTH_CONTROL.fields.6
12575 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, string in object:register_types.DB_DEPTH_CONTROL.fields.7
12599 {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"}, string in object:register_types.DB_DFSM_CONTROL.fields.0
12631 {"bits": [19, 20], "enum_ref": "VRSHtileEncoding", "name": "VRS_HTILE_ENCODING"} string in object:register_types.DB_HTILE_SURFACE.fields.9
12664 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.0
12665 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.1
12666 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.2
12674 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.10
12679 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, string in object:register_types.DB_RENDER_OVERRIDE.fields.15
12691 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.0
12700 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, string in object:register_types.DB_RENDER_OVERRIDE2.fields.9
12736 {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.0
12737 {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.1
12738 {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.2
12739 {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.3
12740 {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.4
12741 {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.5
12742 {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"}, string in object:register_types.DB_RMI_L2_CACHE_CONTROL.fields.6
12756 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, string in object:register_types.DB_SHADER_CONTROL.fields.3
12764 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"}, string in object:register_types.DB_SHADER_CONTROL.fields.11
12774 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE0.fields.0
12782 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, string in object:register_types.DB_SRESULTS_COMPARE_STATE1.fields.0
12811 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.0
12812 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, string in object:register_types.DB_STENCIL_CONTROL.fields.1
12813 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, string in object:register_types.DB_STENCIL_CONTROL.fields.2
12814 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.3
12815 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, string in object:register_types.DB_STENCIL_CONTROL.fields.4
12816 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} string in object:register_types.DB_STENCIL_CONTROL.fields.5
12821 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, string in object:register_types.DB_STENCIL_INFO.fields.0
12823 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, string in object:register_types.DB_STENCIL_INFO.fields.2
12834 {"bits": [0, 2], "enum_ref": "VRSCombinerMode", "name": "VRS_OVERRIDE_RATE_COMBINER_MODE"}, string in object:register_types.DB_VRS_OVERRIDE_CNTL.fields.0
12841 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, string in object:register_types.DB_Z_INFO.fields.0
12844 {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, string in object:register_types.DB_Z_INFO.fields.3
13300 {"bits": [0, 2], "enum_ref": "VRSCombinerMode", "name": "VERTEX_RATE_COMBINER_MODE"}, string in object:register_types.PA_CL_VRS_CNTL.fields.0
13301 {"bits": [3, 5], "enum_ref": "VRSCombinerMode", "name": "PRIMITIVE_RATE_COMBINER_MODE"}, string in object:register_types.PA_CL_VRS_CNTL.fields.1
13302 {"bits": [6, 8], "enum_ref": "VRSCombinerMode", "name": "HTILE_RATE_COMBINER_MODE"}, string in object:register_types.PA_CL_VRS_CNTL.fields.2
13303 {"bits": [9, 11], "enum_ref": "VRSCombinerMode", "name": "SAMPLE_ITER_COMBINER_MODE"}, string in object:register_types.PA_CL_VRS_CNTL.fields.3
13363 {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"}, string in object:register_types.PA_SC_AA_CONFIG.fields.5
13430 {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"}, string in object:register_types.PA_SC_BINNER_CNTL_0.fields.0
13433 {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"}, string in object:register_types.PA_SC_BINNER_CNTL_0.fields.3
13434 {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"}, string in object:register_types.PA_SC_BINNER_CNTL_0.fields.4
13441 {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"} string in object:register_types.PA_SC_BINNER_CNTL_0.fields.11
13482 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} string in object:register_types.PA_SC_CLIPRECT_RULE.fields.0
13497 {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE" string in object:register_types.PA_SC_CONSERVATIVE_RASTERIZATION_CNTL.fields.10
13615 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.0
13616 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.1
13617 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.2
13618 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.3
13619 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.4
13620 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.5
13621 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.6
13622 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.7
13623 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.8
13624 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.9
13625 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.10
13626 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.11
13627 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.12
13628 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG.fields.13
13629 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG.fields.14
13634 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.0
13635 {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.1
13636 {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} string in object:register_types.PA_SC_RASTER_CONFIG_1.fields.2
13797 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, string in object:register_types.PA_SU_SC_MODE_CNTL.fields.3
13798 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_ string in object:register_types.PA_SU_SC_MODE_CNTL.fields.4
13799 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE string in object:register_types.PA_SU_SC_MODE_CNTL.fields.5
13824 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, string in object:register_types.PA_SU_VTX_CNTL.fields.1
13825 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} string in object:register_types.PA_SU_VTX_CNTL.fields.2
13867 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, string in object:register_types.RLC_PERFMON_CNTL.fields.0
14155 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.2
14156 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.3
14157 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.4
14158 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, string in object:register_types.SPI_INTERP_CONTROL_0.fields.5
14237 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.0
14238 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.1
14239 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.2
14240 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.3
14241 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.4
14242 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.5
14243 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_COL_FORMAT.fields.6
14244 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_COL_FORMAT.fields.7
14249 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_IDX_FORMAT.fields.0
14267 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_GS.fields.3
14284 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_HS.fields.3
14300 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_PS.fields.3
14316 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, string in object:register_types.SPI_SHADER_PGM_RSRC1_VS.fields.3
14332 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_GS.fields.3
14345 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_GS_VS.fields.3
14360 {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_HS.fields.5
14373 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_PS.fields.5
14391 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SPI_SHADER_PGM_RSRC2_VS.fields.9
14434 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.0
14435 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.1
14436 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.2
14437 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"}, string in object:register_types.SPI_SHADER_POS_FORMAT.fields.3
14438 {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_POS_FORMAT.fields.4
14460 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} string in object:register_types.SPI_SHADER_Z_FORMAT.fields.0
14490 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.1
14491 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.2
14492 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.3
14493 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.4
14494 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.SQ_PERFCOUNTER_CTRL.fields.5
14569 {"bits": [0, 10], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"}, string in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.0
14571 {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"}, string in object:register_types.SQ_THREAD_TRACE_TOKEN_MASK.fields.2
14672 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, string in object:register_types.SQ_WAVE_MODE.fields.5
14724 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, string in object:register_types.SQ_WAVE_TRAPSTS.fields.0
14767 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"}, string in object:register_types.SX_BLEND_OPT_EPSILON.fields.0
14779 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.0
14780 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.1
14781 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.2
14782 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.3
14783 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"}, string in object:register_types.SX_MRT0_BLEND_OPT.fields.4
14784 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"} string in object:register_types.SX_MRT0_BLEND_OPT.fields.5
14796 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.0
14797 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.1
14798 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.2
14799 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.3
14800 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.4
14801 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.5
14802 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"}, string in object:register_types.SX_PS_DOWNCONVERT.fields.6
14803 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"} string in object:register_types.SX_PS_DOWNCONVERT.fields.7
14836 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.0
14837 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.1
14838 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.2
14839 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, string in object:register_types.VGT_DMA_INDEX_TYPE.fields.3
14849 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.0
14850 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, string in object:register_types.VGT_DRAW_INITIATOR.fields.1
14882 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, string in object:register_types.VGT_EVENT_INITIATOR.fields.0
14899 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, string in object:register_types.VGT_GROUP_PRIM_TYPE.fields.0
14946 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, string in object:register_types.VGT_GS_MODE.fields.0
14948 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, string in object:register_types.VGT_GS_MODE.fields.2
14972 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.0
14973 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.1
14974 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.2
14975 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, string in object:register_types.VGT_GS_OUT_PRIM_TYPE.fields.3
15002 {"bits": [10, 11], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHI string in object:register_types.VGT_HS_OFFCHIP_PARAM_UMD.fields.1
15007 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, string in object:register_types.VGT_INDEX_TYPE.fields.0
15043 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} string in object:register_types.VGT_PRIMITIVE_TYPE.fields.0
15053 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.0
15054 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.1
15055 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.2
15056 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.3
15057 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, string in object:register_types.VGT_SHADER_STAGES_EN.fields.4
15116 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, string in object:register_types.VGT_TF_PARAM.fields.0
15117 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, string in object:register_types.VGT_TF_PARAM.fields.1
15118 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, string in object:register_types.VGT_TF_PARAM.fields.2
15123 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, string in object:register_types.VGT_TF_PARAM.fields.7
15124 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"}, string in object:register_types.VGT_TF_PARAM.fields.8
15125 {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"}, string in object:register_types.VGT_TF_PARAM.fields.9
15126 {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"}, string in object:register_types.VGT_TF_PARAM.fields.10
[all...]

Completed in 631 milliseconds