| /src/sys/dev/sun/ |
| cgthree.c | 168 volatile struct fbcontrol *fbc = sc->sc_fbc; local in function:cgthreeattach
169 volatile struct bt_regs *bt = &fbc->fbc_dac;
178 if ((fbc->fbc_ctrl & FBC_TIMING) == 0) {
179 int sense = (fbc->fbc_status & FBS_MSENSE);
189 fbc->fbc_vcontrol[j] =
191 fbc->fbc_ctrl |= FBC_TIMING;
|
| cgsix.c | 296 #define CG6_DRAIN(fbc) do { \
297 while ((fbc)->fbc_s & GX_INPROGRESS) \
309 #define CG6_WAIT_READY(fbc) do { \
310 while (((fbc)->fbc_s & GX_INPROGRESS/*GX_FULL*/) != 0) \
323 volatile struct cg6_fbc *fbc = sc->sc_fbc; local in function:cg6_ras_init
325 CG6_DRAIN(fbc);
326 fbc->fbc_mode &= ~CG6_MODE_MASK;
327 fbc->fbc_mode |= CG6_MODE;
330 fbc->fbc_clip = 0;
331 fbc->fbc_s = 0
363 volatile struct cg6_fbc *fbc = sc->sc_fbc; local in function:cg6_ras_copyrows
402 volatile struct cg6_fbc *fbc = sc->sc_fbc; local in function:cg6_ras_copycols
449 volatile struct cg6_fbc *fbc = sc->sc_fbc; local in function:cg6_ras_erasecols
478 volatile struct cg6_fbc *fbc = sc->sc_fbc; local in function:cg6_ras_eraserows
1277 volatile struct cg6_fbc *fbc = sc->sc_fbc; local in function:cgsix_rectfill
1297 volatile struct cg6_fbc *fbc = sc->sc_fbc; local in function:cgsix_bitblt
1318 volatile struct cg6_fbc *fbc=sc->sc_fbc; local in function:cgsix_setup_mono
1340 volatile struct cg6_fbc *fbc = sc->sc_fbc; local in function:cgsix_feed_line
1363 volatile struct cg6_fbc *fbc = sc->sc_fbc; local in function:cgsix_putchar
1417 volatile struct cg6_fbc *fbc = sc->sc_fbc; local in function:cgsix_putchar_aa
1554 volatile struct cg6_fbc *fbc = sc->sc_fbc; local in function:cgsix_clearscreen
1574 volatile struct cg6_fbc *fbc = sc->sc_fbc; local in function:cg6_invert
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_fbc.c | 27 * DOC: Frame Buffer Compression (FBC)
29 * FBC tries to save memory bandwidth (and so power consumption) by
33 * The benefits of FBC are mostly visible with solid backgrounds and
37 * i915 is responsible to reserve stolen memory for FBC and configure its
68 static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
70 return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
117 DRM_DEBUG_KMS("FBC idle timed out\n");
124 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
129 /* Note: fbc.threshold == 1 for i8xx *
369 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_hw_activate
386 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_hw_deactivate
415 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_deactivate
477 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_alloc_cfb
538 struct intel_fbc *fbc = &dev_priv->fbc; local in function:__intel_fbc_cleanup_cfb
551 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_cleanup_cfb
614 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_hw_tracking_covers_screen
644 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_update_state_cache
685 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_cfb_size_changed
694 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_can_activate
797 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_can_enable
821 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_get_reg_params
849 const struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_can_flip_nuke
882 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_pre_update
933 struct intel_fbc *fbc = &dev_priv->fbc; local in function:__intel_fbc_disable
950 struct intel_fbc *fbc = &dev_priv->fbc; local in function:__intel_fbc_post_update
980 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_post_update
1002 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_invalidate
1023 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_flush
1062 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_choose_crtc
1122 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_enable
1179 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_disable
1198 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_global_disable
1215 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_underrun_work_fn
1275 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_handle_fifo_underrun_irq
1335 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_init
1370 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_fbc_cleanup
[all...] |
| intel_sprite.c | 2971 struct intel_fbc *fbc = &dev_priv->fbc; local in function:skl_universal_plane_create
2973 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
|
| intel_display.c | 2280 * FBC and the like impose on the size of the buffer, which
3409 * important and we should probably use that space with FBC or other
16165 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
16177 struct intel_fbc *fbc = &dev_priv->fbc; local in function:intel_primary_plane_create
16179 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
|
| /src/sys/dev/ic/ |
| opl.c | 519 u_int8_t chars0, chars1, ksl0, ksl1, fbc; local in function:oplsyn_setv
547 fbc = p->ops[OO_FB_CONN];
549 fbc &= ~OPL_STEREO_BITS;
550 fbc |= sc->pan[chan];
552 opl_set_ch_reg(sc, OPL_FEEDBACK_CONNECTION, voice, fbc);
|
| /src/sys/arch/sparc64/dev/ |
| ffb.c | 628 uint32_t fbc; local in function:ffb_ras_init
632 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON |
636 fbc = FFB_FBC_XE_OFF;
646 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH |
648 DPRINTF(("%s: fbc is %08x\n", __func__, fbc));
649 FBC_WRITE(sc, FFB_FBC_FBC, fbc);
1498 /* Pixel Format Control, User Control and FBC Configuration. */
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_debugfs.c | 1242 struct intel_fbc *fbc = &dev_priv->fbc; local in function:i915_fbc_status
1249 mutex_lock(&fbc->lock);
1252 seq_puts(m, "FBC enabled\n");
1254 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
1274 mutex_unlock(&fbc->lock);
1287 *val = dev_priv->fbc.false_color;
1300 mutex_lock(&dev_priv->fbc.lock);
1303 dev_priv->fbc.false_color = val
[all...] |
| intel_pm.c | 950 * in the actual pixel depth regardless of whether FBC is enabled or not."
974 FW_WM(wm->sr.fbc, FBC_SR) |
975 FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
1204 /* NORMAL level doesn't have an FBC watermark */
1210 dirty |= raw->fbc != value;
1211 raw->fbc = value;
1260 * FBC wm is not mandatory as we
1266 dirty |= raw->fbc != wm;
1267 raw->fbc = wm;
1287 "FBC watermarks: SR=%d, HPLL=%d\n"
2522 u16 fbc; member in struct:ilk_wm_maximums
[all...] |
| i915_drv.h | 428 * and re-enable FBC for a new configuration we just check if there's
763 u16 fbc; member in struct:g4x_pipe_wm
769 u16 fbc; member in struct:g4x_sr_wm
1004 struct intel_fbc fbc; member in struct:drm_i915_private
|
