| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dp_link_training.c | 48 int lane; local in function:intel_get_adjust_train
52 for (lane = 0; lane < intel_dp->lane_count; lane++) {
53 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
54 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
70 for (lane = 0; lane < 4; lane++)
71 intel_dp->train_set[lane] = v | p
124 int lane; local in function:intel_dp_link_max_vswing_reached
[all...] |
| intel_dpio_phy.c | 47 * houses a common lane part which contains the PLL and other common
48 * logic. CH0 common lane also contains the IOSF-SB logic for the
63 * Additionally the PHY also contains an AUX lane with AUX blocks
69 * Generally on VLV/CHV the common lane corresponds to the pipe and
284 * can read only lane registers and we pick lanes 0/1 for that.
602 int lane; local in function:bxt_ddi_phy_set_lane_optim_mask
606 for (lane = 0; lane < 4; lane++) {
607 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
628 int lane; local in function:bxt_ddi_phy_get_lane_lat_optim_mask
[all...] |
| icl_dsi.c | 213 int lane; local in function:dsi_program_swing_and_deemphasis
258 for (lane = 0; lane <= 3; lane++) {
260 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
266 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
398 int lane; local in function:gen11_dsi_config_phy_lanes_sequence
405 for (lane = 0; lane <= 3; lane++)
[all...] |
| intel_display.c | 7649 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7682 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7716 int lane, link_bw, fdi_dotclock, ret; local in function:ilk_fdi_compute_config
7724 * Hence the bw of each lane in terms of the mode signal
7731 lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
7734 pipe_config->fdi_lanes = lane;
7736 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
|
| /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_pwhash/argon2/ |
| argon2-core.h | 115 uint32_t lane; member in struct:Argon2_position_t
130 * Computes absolute position of reference block in the lane following a skewed
135 * @param same_lane Indicates if the block will be taken from the current lane.
145 * This lane : all already finished segments plus already constructed
149 * This lane : (SYNC_POINTS - 1) last segments plus already constructed
165 /* The same lane => add current segment */
233 * Function creates first 2 blocks per lane
242 * two blocks. Returns the pointer to the main memory with 2 blocks per lane
258 * XORing the last block of each lane, hashing it, making the tag. Deallocates
291 * blocks in each lane
[all...] |
| /src/sys/arch/arm/rockchip/ |
| rk3399_pcie_phy.c | 120 uint8_t * const lane = priv; local in function:rkpciephy_phy_enable
122 // device_printf(dev, "%s %u %u\n", __func__, *lane, enable);
125 rkpcie_phy_poweron(sc, *lane);
126 sc->sc_phys_on |= 1U << *lane;
129 sc->sc_phys_on &= ~(1U << *lane);
202 rkpcie_phy_poweron(struct rkpciephy_softc *sc, u_int lane)
219 RK3399_TX_ELEC_IDLE_OFF_MASK << lane | 0);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_dp.c | 93 u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; local in function:nvkm_dp_train_drive
95 u8 lpre = (lane & 0x0c) >> 2;
96 u8 lvsw = (lane & 0x03) >> 0;
114 OUTP_TRACE(&dp->outp, "config lane %d %02x %02x",
180 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; local in function:nvkm_dp_train_eq
181 if (!(lane & DPCD_LS02_LANE0_CR_DONE))
183 if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
184 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
208 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; local in function:nvkm_dp_train_cr
209 if (!(lane & DPCD_LS02_LANE0_CR_DONE))
494 u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f; local in function:nvkm_dp_acquire
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_atombios_dp.c | 217 int lane; local in function:amdgpu_atombios_dp_get_adjust_train
219 for (lane = 0; lane < lane_count; lane++) {
220 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
221 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
223 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
224 lane,
244 for (lane = 0; lane < 4; lane++
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_link_encoder.c | 1089 * by checking lane count that has been set
1119 int32_t lane = 0; local in function:dce110_link_encoder_dp_set_lane_settings
1135 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1136 /* translate lane settings */
1139 link_settings->lane_settings[lane].VOLTAGE_SWING;
1141 link_settings->lane_settings[lane].PRE_EMPHASIS;
1149 link_settings->lane_settings[lane].POST_CURSOR2;
1152 cntl.lane_select = lane;
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_link_encoder.c | 1054 * by checking lane count that has been set
1085 int32_t lane = 0; local in function:dcn10_link_encoder_dp_set_lane_settings
1101 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1102 /* translate lane settings */
1105 link_settings->lane_settings[lane].VOLTAGE_SWING;
1107 link_settings->lane_settings[lane].PRE_EMPHASIS;
1115 link_settings->lane_settings[lane].POST_CURSOR2;
1118 cntl.lane_select = lane;
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_atombios_dp.c | 275 int lane; local in function:dp_get_adjust_train
277 for (lane = 0; lane < lane_count; lane++) {
278 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
279 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
281 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
282 lane,
302 for (lane = 0; lane < 4; lane++
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_dp_helper.c | 62 int lane)
64 int i = DP_LANE0_1_STATUS + (lane >> 1);
65 int s = (lane & 1) * 4;
75 int lane; local in function:drm_dp_channel_eq_ok
81 for (lane = 0; lane < lane_count; lane++) {
82 lane_status = dp_get_lane_status(link_status, lane);
93 int lane; local in function:drm_dp_clock_recovery_ok
96 for (lane = 0; lane < lane_count; lane++)
[all...] |
| /src/sys/arch/arm/nvidia/ |
| tegra210_xusbpad.c | 663 tegra210_xusbpad_find_func(const struct tegra210_xusbpad_lane *lane,
666 for (int n = 0; n < lane->nfuncs; n++)
667 if (strcmp(lane->funcs[n], func) == 0)
685 const struct tegra210_xusbpad_lane *lane; local in function:tegra210_xusbpad_configure_lane
700 lane = tegra210_xusbpad_find_lane(name);
701 if (lane == NULL) {
702 aprint_error_dev(sc->sc_dev, "unsupported lane '%s'\n", name);
705 func = tegra210_xusbpad_find_func(lane, function);
711 aprint_normal_dev(sc->sc_dev, "lane %s: set func %s\n", name, function);
712 SETCLR4(sc, lane->reg, __SHIFTIN(func, lane->mask), lane->mask)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_dp.c | 175 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
185 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
245 uint32_t lane; local in function:dpcd_set_lt_pattern_and_lane_settings
278 for (lane = 0; lane <
279 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
281 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
282 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
283 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
284 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS)
354 uint32_t lane; local in function:is_cr_done
369 uint32_t lane; local in function:is_ch_eq_done
387 uint32_t lane; local in function:update_drive_settings
437 uint32_t lane; local in function:find_max_drive_settings
541 uint32_t lane; local in function:get_lane_status_and_drive_settings
648 uint32_t lane; local in function:dpcd_set_lane_settings
728 uint32_t lane; local in function:is_max_vs_reached
750 uint32_t lane; local in function:perform_post_lt_adj_req_sequence
1107 uint32_t lane; local in function:initialize_training_settings
1796 uint32_t lane; local in function:hpd_rx_irq_check_link_loss_status
2507 unsigned int lane; local in function:dp_test_send_phy_test_pattern
3797 unsigned int lane; local in function:dc_link_dp_set_test_pattern
[all...] |
