| /src/sys/arch/arm/at91/ |
| at91pmc.c | 55 uint64_t mclk, pllaclk, pllbclk, pclk, mstclk; local
64 mclk = ((reg & PMC_MCFR_MAINF) * SLOW_CLOCK) / 16U;
67 if (((mclk / 1000) % 1000) >= 990) {
68 mclk += 1000000U - (mclk % 1000000U);
69 } else if (((mclk / 1000) % 1000) <= 10) {
70 mclk -= (mclk % 1000000U);
77 pllaclk = mclk * (((reg & PMC_PLL_MUL) >> PMC_PLL_MUL_SHIFT) + 1);
83 pllbclk = mclk * (((reg & PMC_PLL_MUL) >> PMC_PLL_MUL_SHIFT) + 1)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_clocks.c | 78 uint32_t fb_div, ref_div, post_div, mclk; local
91 mclk = fb_div / ref_div;
95 mclk >>= 1;
97 mclk >>= 2;
99 mclk >>= 3;
101 return mclk;
106 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
167 val = of_get_property(dp, "ATY,MCLK", NULL);
|
| rv6xx_dpm.h | 83 u32 mclk; member in struct:rv6xx_pl
|
| radeon_device.c | 752 * Used when sclk/mclk are switched or display modes are set.
759 u32 mclk = rdev->pm.current_mclk; local
761 /* sclk/mclk in Mhz */
765 rdev->pm.mclk.full = dfixed_const(mclk);
766 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
|
| radeon_pm.c | 191 u32 sclk, mclk; local
206 * mclk and vddci.
213 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
214 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
216 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
217 clock_info[rdev->pm.requested_clock_mode_index].mclk;
219 if (mclk > rdev->pm.default_mclk)
220 mclk = rdev->pm.default_mclk;
249 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
251 radeon_set_memory_clock(rdev, mclk);
[all...] |
| rv770_smc.h | 111 RV7XX_SMC_MCLK_VALUE mclk; member in struct:RV770_SMC_HW_PERFORMANCE_LEVEL
|
| rv770_dpm.h | 146 u32 mclk; member in struct:rv7xx_pl
187 LPRV7XX_SMC_MCLK_VALUE mclk);
208 RV7XX_SMC_MCLK_VALUE *mclk);
222 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
|
| ci_dpm.h | 42 u32 mclk; member in struct:ci_pl
|
| nislands_smc.h | 111 NISLANDS_SMC_MCLK_VALUE mclk; member in struct:NISLANDS_SMC_HW_PERFORMANCE_LEVEL
|
| radeon_btc_dpm.c | 1249 u32 *sclk, u32 *mclk)
1253 if ((sclk == NULL) || (mclk == NULL))
1260 (btc_blacklist_clocks[i].mclk == *mclk))
1269 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk);
1279 if ((pl->mclk == 0) || (pl->sclk == 0))
1282 if (pl->mclk == pl->sclk)
1285 if (pl->mclk > pl->sclk) {
1286 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio)
1289 (pl->mclk
2106 u32 mclk, sclk; local
[all...] |
| radeon_combios.c | 747 uint16_t sclk, mclk; local
800 /* default sclk/mclk */
802 mclk = RBIOS16(pll_info + 0x8);
805 if (mclk == 0)
806 mclk = 200 * 100;
809 rdev->clock.default_mclk = mclk;
2742 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2744 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2816 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
|
| radeon_kv_dpm.c | 1988 table->mclk = pi->sys_info.nbp_memory_clock[0];
2152 u32 sclk, mclk = 0; local
2169 mclk = max_limits->mclk;
2250 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2294 u32 mclk = max_limits->mclk; local
2309 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2723 rdev->pm.dpm.vce_states[i].mclk = 0;
|
| /src/sys/arch/mips/ingenic/ |
| apbus.c | 129 uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv, cclk, cdiv; local
148 mclk = (48000 * (m + 1) / (n + 1)) / (p + 1);
152 pclk = mclk / pdiv;
154 cclk = mclk / cdiv;
156 aprint_debug_dev(self, "mclk %d kHz\n", mclk);
252 aa.aa_mclk = mclk;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_atombios.h | 98 u32 mclk[MAX_AC_TIMING_ENTRIES]; member in struct:atom_memory_clock_range_table
|
| amdgpu_pm.c | 297 * to the lowest level. profile_min_mclk forces the mclk to the lowest level.
298 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
677 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
683 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
700 * - a list of valid ranges for sclk, mclk, and voltage curve points
711 * "m 1 800" will update maximum mclk to be 800Mhz.
969 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
2601 uint32_t mclk; local
2602 int r, size = sizeof(mclk);
2610 (void *)&mclk, &size)
[all...] |
| amdgpu_dpm.h | 109 u32 mclk; member in struct:amdgpu_blacklist_clocks
115 u32 mclk; member in struct:amdgpu_clock_and_voltage_limits
155 u32 mclk; member in struct:amdgpu_phase_shedding_limits_entry
|
| amdgpu_kv_dpm.c | 2054 table->mclk = pi->sys_info.nbp_memory_clock[0];
2217 u32 sclk, mclk = 0; local
2234 mclk = max_limits->mclk;
2315 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2359 u32 mclk = max_limits->mclk; local
2374 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2791 adev->pm.dpm.vce_states[i].mclk = 0;
|
| sislands_smc.h | 156 SISLANDS_SMC_MCLK_VALUE mclk; member in struct:SISLANDS_SMC_HW_PERFORMANCE_LEVEL
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services_types.h | 66 struct dm_pp_clock_range mclk; member in struct:dm_pp_gpu_clock_range
208 /*Controller Index of primary display - used in MCLK SMC switching hang
211 /*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_smu10_hwmgr.c | 1127 uint32_t sclk, mclk; local
1140 mclk = smum_get_argument(hwmgr);
1142 *((uint32_t *)value) = mclk * 100;
|
| ppatomctrl.h | 198 uint32_t mclk[MAX_AC_TIMING_ENTRIES]; member in struct:pp_atomctrl_memory_clock_range_table
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| power_state.h | 180 unsigned long mclk; member in struct:pp_clock_engine_request
|
| /src/sys/external/bsd/drm2/dist/drm/ast/ |
| ast_drv.h | 116 uint32_t mclk; member in struct:ast_private
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| nouveau_nvkm_subdev_fb_ramgt215.c | 461 gt215_ram_lock_pll(struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk)
463 ram_wr32(fuc, 0x004004, mclk->pll);
505 struct gt215_clk_info mclk; local
556 ret = gt215_pll_info(device->clk, 0x12, 0x4000, freq, &mclk);
558 nvkm_error(subdev, "failed mclk calculation\n");
607 pll2pll = (!(ctrl & 0x00000008)) && mclk.pll;
620 if (mclk.pll && !pll2pll) {
621 ram_mask(fuc, 0x004128, 0x003f3141, mclk.clk | 0x00000101);
622 gt215_ram_lock_pll(fuc, &mclk);
696 gt215_ram_lock_pll(fuc, &mclk);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| kgd_pp_interface.h | 37 u32 mclk; member in struct:amd_vce_state
|
