1 /* $NetBSD: rv770_smc.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __RV770_SMC_H__ 26 #define __RV770_SMC_H__ 27 28 #include "ppsmc.h" 29 30 #pragma pack(push, 1) 31 32 #define RV770_SMC_TABLE_ADDRESS 0xB000 33 34 #define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 3 35 36 struct RV770_SMC_SCLK_VALUE 37 { 38 uint32_t vCG_SPLL_FUNC_CNTL; 39 uint32_t vCG_SPLL_FUNC_CNTL_2; 40 uint32_t vCG_SPLL_FUNC_CNTL_3; 41 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 42 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 43 uint32_t sclk_value; 44 }; 45 46 typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE; 47 48 struct RV770_SMC_MCLK_VALUE 49 { 50 uint32_t vMPLL_AD_FUNC_CNTL; 51 uint32_t vMPLL_AD_FUNC_CNTL_2; 52 uint32_t vMPLL_DQ_FUNC_CNTL; 53 uint32_t vMPLL_DQ_FUNC_CNTL_2; 54 uint32_t vMCLK_PWRMGT_CNTL; 55 uint32_t vDLL_CNTL; 56 uint32_t vMPLL_SS; 57 uint32_t vMPLL_SS2; 58 uint32_t mclk_value; 59 }; 60 61 typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE; 62 63 64 struct RV730_SMC_MCLK_VALUE 65 { 66 uint32_t vMCLK_PWRMGT_CNTL; 67 uint32_t vDLL_CNTL; 68 uint32_t vMPLL_FUNC_CNTL; 69 uint32_t vMPLL_FUNC_CNTL2; 70 uint32_t vMPLL_FUNC_CNTL3; 71 uint32_t vMPLL_SS; 72 uint32_t vMPLL_SS2; 73 uint32_t mclk_value; 74 }; 75 76 typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE; 77 78 struct RV770_SMC_VOLTAGE_VALUE 79 { 80 uint16_t value; 81 uint8_t index; 82 uint8_t padding; 83 }; 84 85 typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE; 86 87 union RV7XX_SMC_MCLK_VALUE 88 { 89 RV770_SMC_MCLK_VALUE mclk770; 90 RV730_SMC_MCLK_VALUE mclk730; 91 }; 92 93 typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE; 94 95 struct RV770_SMC_HW_PERFORMANCE_LEVEL 96 { 97 uint8_t arbValue; 98 union{ 99 uint8_t seqValue; 100 uint8_t ACIndex; 101 }; 102 uint8_t displayWatermark; 103 uint8_t gen2PCIE; 104 uint8_t gen2XSP; 105 uint8_t backbias; 106 uint8_t strobeMode; 107 uint8_t mcFlags; 108 uint32_t aT; 109 uint32_t bSP; 110 RV770_SMC_SCLK_VALUE sclk; 111 RV7XX_SMC_MCLK_VALUE mclk; 112 RV770_SMC_VOLTAGE_VALUE vddc; 113 RV770_SMC_VOLTAGE_VALUE mvdd; 114 RV770_SMC_VOLTAGE_VALUE vddci; 115 uint8_t reserved1; 116 uint8_t reserved2; 117 uint8_t stateFlags; 118 uint8_t padding; 119 }; 120 121 #define SMC_STROBE_RATIO 0x0F 122 #define SMC_STROBE_ENABLE 0x10 123 124 #define SMC_MC_EDC_RD_FLAG 0x01 125 #define SMC_MC_EDC_WR_FLAG 0x02 126 #define SMC_MC_RTT_ENABLE 0x04 127 #define SMC_MC_STUTTER_EN 0x08 128 129 typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL; 130 131 struct RV770_SMC_SWSTATE 132 { 133 uint8_t flags; 134 uint8_t padding1; 135 uint8_t padding2; 136 uint8_t padding3; 137 RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 138 }; 139 140 typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE; 141 142 #define RV770_SMC_VOLTAGEMASK_VDDC 0 143 #define RV770_SMC_VOLTAGEMASK_MVDD 1 144 #define RV770_SMC_VOLTAGEMASK_VDDCI 2 145 #define RV770_SMC_VOLTAGEMASK_MAX 4 146 147 struct RV770_SMC_VOLTAGEMASKTABLE 148 { 149 uint8_t highMask[RV770_SMC_VOLTAGEMASK_MAX]; 150 uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX]; 151 }; 152 153 typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE; 154 155 #define MAX_NO_VREG_STEPS 32 156 157 struct RV770_SMC_STATETABLE 158 { 159 uint8_t thermalProtectType; 160 uint8_t systemFlags; 161 uint8_t maxVDDCIndexInPPTable; 162 uint8_t extraFlags; 163 uint8_t highSMIO[MAX_NO_VREG_STEPS]; 164 uint32_t lowSMIO[MAX_NO_VREG_STEPS]; 165 RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable; 166 RV770_SMC_SWSTATE initialState; 167 RV770_SMC_SWSTATE ACPIState; 168 RV770_SMC_SWSTATE driverState; 169 RV770_SMC_SWSTATE ULVState; 170 }; 171 172 typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE; 173 174 #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 175 176 #pragma pack(pop) 177 178 #define RV770_SMC_SOFT_REGISTERS_START 0x104 179 180 #define RV770_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0 181 #define RV770_SMC_SOFT_REGISTER_baby_step_timer 0x8 182 #define RV770_SMC_SOFT_REGISTER_delay_bbias 0xC 183 #define RV770_SMC_SOFT_REGISTER_delay_vreg 0x10 184 #define RV770_SMC_SOFT_REGISTER_delay_acpi 0x2C 185 #define RV770_SMC_SOFT_REGISTER_seq_index 0x64 186 #define RV770_SMC_SOFT_REGISTER_mvdd_chg_time 0x68 187 #define RV770_SMC_SOFT_REGISTER_mclk_switch_lim 0x78 188 #define RV770_SMC_SOFT_REGISTER_mc_block_delay 0x90 189 #define RV770_SMC_SOFT_REGISTER_uvd_enabled 0x9C 190 #define RV770_SMC_SOFT_REGISTER_is_asic_lombok 0xA0 191 192 int rv770_copy_bytes_to_smc(struct radeon_device *rdev, 193 u16 smc_start_address, const u8 *src, 194 u16 byte_count, u16 limit); 195 void rv770_start_smc(struct radeon_device *rdev); 196 void rv770_reset_smc(struct radeon_device *rdev); 197 void rv770_stop_smc_clock(struct radeon_device *rdev); 198 void rv770_start_smc_clock(struct radeon_device *rdev); 199 bool rv770_is_smc_running(struct radeon_device *rdev); 200 PPSMC_Result rv770_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg); 201 PPSMC_Result rv770_wait_for_smc_inactive(struct radeon_device *rdev); 202 int rv770_read_smc_sram_dword(struct radeon_device *rdev, 203 u16 smc_address, u32 *value, u16 limit); 204 int rv770_write_smc_sram_dword(struct radeon_device *rdev, 205 u16 smc_address, u32 value, u16 limit); 206 int rv770_load_smc_ucode(struct radeon_device *rdev, 207 u16 limit); 208 209 #endif 210
Indexes created Fri Sep 26 20:09:58 GMT 2025