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    Searched defs:mclk (Results 1 - 22 of 22) sorted by relevancy

  /xsrc/external/mit/xf86-video-s3/dist/src/
s3_Trio64DAC.c 284 int m, n, n1, n2, mclk; local
298 mclk = ((1431818 * (m+2)) / (n1+2) / (1<<n2)+50)/100;
304 mclk /= ((SR27 >> 2) & 0x03) + 1;
306 pS3->mclk = mclk;
311 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "MCLK %1.3f Mhz\n",
312 mclk / 1000.0);
s3_GENDAC.c 160 int m, n, n1, n2, mclk; local
166 outb(0x3C7, 10); /* read MCLK */
176 mclk = ((1431818 * (m + 2)) / (n1 + 2) / (1 << n2) + 50) / 100;
178 pS3->mclk = mclk;
179 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "MCLK %1.3f MHz\n",
180 mclk / 1000.0);
s3_IBMRGB.c 274 int m, n, df, mclk=0; local
284 mclk = ((pS3->RefClock*100 * (m+65)) / n / (8 >> df) + 50) / 100;
285 pS3->mclk = mclk;
286 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "MCLK %1.3f MHz\n",
287 mclk / 1000.0);
s3_Ti.c 322 int mclk, m, n, p, mcc, cr5c; local
340 mclk = ((1431818 * ((m+2) * 8)) / (n+2) / (1 << p) / mcc + 50) / 100;
341 pS3->mclk = mclk;
342 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "MCLK %1.3f MHz\n",
343 mclk / 1000.0);
s3_driver.c 1519 int clock2, mclk; local
1524 mclk = pS3->mclk;
1525 m = (int)((mclk/1000.0*.72+16.867)*89.736/(clock2/1000.0+39)-21.1543);
s3.h 159 int mclk, MaxClock; member in struct:_S3Rec
  /xsrc/external/mit/xf86-video-siliconmotion/dist/src/
smi_501.c 203 if (pSmi->MCLK) {
205 "MCLK request %d\n", pSmi->MCLK);
206 (void)SMI501_FindMemClock(pSmi->MCLK, &x_select, &x_divider, &x_shift);
249 if (pSmi->MCLK) {
455 double diff, best, mclk; local
464 for (multiplier = 12, mclk = multiplier * 24 * 1000.0;
465 mclk <= 14 * 24 * 1000.0;
466 multiplier += 2, mclk = multiplier * 24 * 1000.0) {
471 diff = (mclk / (divider << shift << xclck)) - clock
500 double diff, best, mclk; local
    [all...]
smi_driver.c 186 { OPTION_MCLK, "MCLK", OPTV_FREQ, {0}, FALSE },
1140 int mclk, mxclk; local
1143 /* MCLK defaults */
1147 pSmi->MCLK = 157000;
1155 pSmi->MCLK = 112000;
1160 pSmi->MCLK = 0;
1164 /* MCLK from user settings */
1167 pSmi->MCLK = (int)(real * 1000.0);
1174 mclk = pSmi->MCLK;
    [all...]
  /xsrc/external/mit/xf86-video-sis/dist/src/
sis_setup.c 64 /* MCLK tables for SiS6326 */
73 CARD16 mclk; member in struct:_sis6326mclk
294 pSiS->MemClock = SiS6326MCLK[i].mclk;
296 /* Correct invalid MCLK settings by old BIOSes */
459 "(Adapter assumes MCLK being %d Mhz)\n",
465 "(Adapter assumes MCLK being %d Mhz)\n",
894 /* DDR -> Mclk * 2 - needed for bandwidth calculation */
sis_dac.c 1282 /* Not for 530/620 if UMA (on these, the mclk is stored in SR10) */
1286 int mclk=0; local
1307 mclk = 14318 * ((Num & 0x7f) + 1);
1311 mclk = mclk / ((Denum & 0x1f) + 1);
1314 if((Num & 0x80) != 0) mclk *= 2;
1318 mclk = mclk / (((Denum & 0x60) >> 5) + 1);
1320 mclk = mclk / ((((Denum & 0x60) >> 5) + 1) * 2)
1440 int mclk = pSiS->MemClock; local
    [all...]
sis_vga.c 181 int mclk = pSiS->MemClock; local
660 mclk = 14318 * ((pReg->sisRegs3C4[0x28] & 0x7f) + 1);
661 mclk /= ((pReg->sisRegs3C4[0x29] & 0x0f) + 1);
663 mclk /= (((pReg->sisRegs3C4[0x29] & 0x60) >> 5) + 1);
665 if((pReg->sisRegs3C4[0x29] & 0x60) == 0x40) mclk /= 6;
666 if((pReg->sisRegs3C4[0x29] & 0x60) == 0x60) mclk /= 8;
670 mclk/1000.0);
679 * MCLK ___________ VCLK
707 b = (mclk / 1000) * 999488.0 * (buswidth / 8);
723 (mclk == 100000) &
    [all...]
  /xsrc/external/mit/xf86-video-tseng/dist/src/
tseng_mode.c 756 int mclk; local
762 mclk = (ET6000IORead(pTseng, 0x69) + 2) * 14318;
764 mclk /= ((dbyte & 0x1f) + 2) * (1 << ((dbyte >> 5) & 0x03));
765 pTseng->MemClk = mclk;
1117 /* save MClk values */
1169 /* set MClk values if needed, but don't touch them if not needed
1171 * Since setting the MClk to highly illegal value results in a
1176 xf86Msg(X_ERROR, "Internal Error in MClk registers: MClk: 0x%04X\n",
1427 /* according to Tseng Labs, N1 must be <= 4, and N2 should always be 1 for MClk */
    [all...]
  /xsrc/external/mit/xf86-video-xgi/dist/src/
xgi_dac.c 494 const int mclk = pXGI->MemClock; local
497 float total = (mclk * bus) / bpp;
499 PDEBUG5(ErrorF("mclk: %d, bus: %d, magic: %f, bpp: %d\n",
500 mclk, bus, magic, bpp));
521 const int mclk = pXGI->MemClock; local
524 float total = (mclk * bus) / bpp;
529 PDEBUG5(ErrorF("mclk: %d, bus: %d, magic: %f, bpp: %d\n",
530 mclk, bus, magic, bpp));
532 total = mclk*bus/bpp;
722 int mclk; local
    [all...]
  /xsrc/external/mit/xf86-video-ati/dist/src/
atombios_crtc.c 1171 * READ_DLY_MAX_LATENCY: 370 * MCLK + 800 ns
1172 * MCLK is the sideport memory clock period in ns (MCLK = 1000 / MCLKfreq MHz)
1180 float mclk = 1000 / info->igp_sideport_mclk; local
1181 read_delay_latency = 370 * mclk * 800;
radeon.h 430 uint32_t mclk; member in struct:__anon6810
862 float mclk; /* in MHz */ member in struct:__anon6814
  /xsrc/external/mit/xf86-video-i128/dist/src/
i128_driver.c 445 float mclk; local
877 mclk = ((1431818 * ((m+2) * 8)) / (n+2) / (1 << p) / mdc + 50) / 100;
880 "Using TI 3025 programmable clock (MCLK %1.3f MHz)\n",
881 mclk / 1000.0);
908 mclk = ((2517500 * (m+65)) / n / (8>>df) + 50) / 100;
919 "Using IBM 526 programmable clock (MCLK %1.3f MHz)\n",
920 mclk / 1000.0);
942 mclk = ((2517500 * (m+65)) / n / (8>>df) + 50) / 100;
953 "Using IBM 528 programmable clock (MCLK %1.3f MHz)\n",
954 mclk / 1000.0)
    [all...]
  /xsrc/external/mit/xf86-video-s3virge/dist/src/
s3v_driver.c 485 int mclk; local
705 ps3v->MCLK = (int)(real * 1000.0);
706 if (ps3v->MCLK <= 100000) {
708 ps3v->MCLK / 1000.0 );
712 , ps3v->MCLK/1000.0);
713 ps3v->MCLK = 0;
716 ps3v->MCLK = 0;
1102 if (ps3v->MCLK <= 0)
1103 ps3v->MCLK = 74000;
1112 /* Detect current MCLK and print it for user *
    [all...]
  /xsrc/external/mit/xf86-video-trident/dist/src/
trident_driver.c 672 /* MCLK Init */
1860 float mclk; local
3046 pTrident->MCLK = 0;
3047 mclk = CalculateMCLK(pScrn);
3048 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Memory Clock is %3.2f MHz\n", mclk);
3051 pTrident->MCLK = (int)(real * 1000.0);
3053 (float)(pTrident->MCLK / 1000));
  /xsrc/external/mit/xf86-video-savage/dist/src/
savage_driver.c 1090 int mclk; local
2035 /* detect current mclk */
2048 mclk = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
2049 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "Detected current MCLK value of %1.3f MHz\n",
2050 mclk / 1000.0);
2826 /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates that
2856 /* load new m, n pll values for dclk & mclk */
3867 if (psav->MCLK <= 0) {
  /xsrc/external/mit/xf86-video-chips/dist/src/
ct_driver.c 2168 int mclk = (int)(real * 1000.0); local
2169 if (mclk <= MemClk->Max) {
2172 (float)(mclk/1000.));
2177 if ((mclk - MemClk->ProbedClk) > 50U) {
2180 MemClk->Clk = mclk;
2193 (float)(mclk/1000.),
3471 /* max VCLK is 80 MHz, max MCLK is 75 MHz for CT65548 */
3565 /* max MCLK is 75 MHz for CT65548 */
3580 int mclk = (int)(real * 1000.0); local
3581 if (mclk <= cPtr->MemClock.Max)
    [all...]
  /xsrc/external/mit/MesaLib/dist/include/drm-uapi/
amdgpu_drm.h 1088 __u32 mclk; member in struct:drm_amdgpu_info_vce_clock_table_entry
  /xsrc/external/mit/libdrm/dist/include/drm/
amdgpu_drm.h 1523 __u32 mclk; member in struct:drm_amdgpu_info_vce_clock_table_entry

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