| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/compiler/ |
| radeon_opcodes.c | 37 .Opcode = RC_OPCODE_NOP,
41 .Opcode = RC_OPCODE_ILLEGAL_OPCODE,
42 .Name = "ILLEGAL OPCODE"
45 .Opcode = RC_OPCODE_ABS,
52 .Opcode = RC_OPCODE_ADD,
59 .Opcode = RC_OPCODE_ARL,
65 .Opcode = RC_OPCODE_ARR,
71 .Opcode = RC_OPCODE_CEIL,
78 .Opcode = RC_OPCODE_CLAMP,
85 .Opcode = RC_OPCODE_CMP
535 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/compiler/ |
| radeon_opcodes.c | 35 .Opcode = RC_OPCODE_NOP,
39 .Opcode = RC_OPCODE_ILLEGAL_OPCODE,
40 .Name = "ILLEGAL OPCODE"
43 .Opcode = RC_OPCODE_ABS,
50 .Opcode = RC_OPCODE_ADD,
57 .Opcode = RC_OPCODE_ARL,
63 .Opcode = RC_OPCODE_ARR,
69 .Opcode = RC_OPCODE_CEIL,
76 .Opcode = RC_OPCODE_CLAMP,
83 .Opcode = RC_OPCODE_CMP
533 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| /xsrc/external/mit/xf86-video-ati/dist/src/AtomBios/ |
| Decoder.c | 59 UINT8 opcode=((COMMAND_HEADER*)pParserTempData->pWorkingTableData->IP)->Opcode; local
60 pParserTempData->pWorkingTableData->IP+=CallTable[opcode].headersize;
61 pParserTempData->ParametersType.Destination=CallTable[opcode].destination;
65 return opcode;
213 if (IS_COMMAND_VALID(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode))
217 if (IS_END_OF_TABLE(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode))
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| r700_asm.c | 130 unsigned opcode = r600_isa_fetch_opcode(bc->isa->hw_class, mem->op) >> 8; local
135 S_SQ_MEM_RD_WORD0_MEM_OP(opcode) |
|
| eg_asm.c | 40 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op); local
65 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
74 bc->bytecode[id] = S_SQ_CF_WORD1_CF_INST(opcode) |
96 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode);
113 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
131 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
140 bc->bytecode[id] = S_SQ_CF_WORD1_CF_INST(opcode) |
229 unsigned opcode; local
231 opcode = 5;
234 opcode = 4
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| r700_asm.c | 130 unsigned opcode = r600_isa_fetch_opcode(bc->isa->hw_class, mem->op) >> 8; local
135 S_SQ_MEM_RD_WORD0_MEM_OP(opcode) |
|
| eg_asm.c | 40 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op); local
65 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
74 bc->bytecode[id] = S_SQ_CF_WORD1_CF_INST(opcode) |
96 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode);
113 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
131 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
140 bc->bytecode[id] = S_SQ_CF_WORD1_CF_INST(opcode) |
229 unsigned opcode; local
231 opcode = 5;
234 opcode = 4
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| si_pm4.c | 30 static void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
33 state->last_opcode = opcode;
53 unsigned opcode; local
58 opcode = PKT3_SET_CONFIG_REG;
62 opcode = PKT3_SET_SH_REG;
66 opcode = PKT3_SET_CONTEXT_REG;
70 opcode = PKT3_SET_UCONFIG_REG;
82 if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
83 si_pm4_cmd_begin(state, opcode);
|
| /xsrc/external/mit/MesaLib/dist/src/intel/common/ |
| intel_disasm.c | 32 is_send(uint32_t opcode)
34 return (opcode == BRW_OPCODE_SEND ||
35 opcode == BRW_OPCODE_SENDC ||
36 opcode == BRW_OPCODE_SENDS ||
37 opcode == BRW_OPCODE_SENDSC );
46 /* This loop exits when send-with-EOT or when opcode is 0 */
57 uint32_t opcode = brw_inst_opcode(devinfo, insn); local
58 if (opcode == 0 || (is_send(opcode) && brw_inst_eot(devinfo, insn))) {
|
| /xsrc/external/mit/libxcb/dist/src/ |
| xcbext.h | 50 uint8_t opcode; member in struct:__anon6373
|
| /xsrc/external/mit/xorg-server/dist/test/bigreq/ |
| request-length.c | 38 uint8_t opcode; member in struct:__anon10312
46 .opcode = XCB_INPUT_XI_SELECT_EVENTS,
|
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| radv_cs.h | 122 unsigned opcode = PKT3_SET_SH_REG_INDEX; local
124 opcode = PKT3_SET_SH_REG;
126 radeon_emit(cs, PKT3(opcode, 1, 0));
166 unsigned opcode = PKT3_SET_UCONFIG_REG_INDEX; local
169 opcode = PKT3_SET_UCONFIG_REG;
171 radeon_emit(cs, PKT3(opcode, 1, 0));
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/rbug/ |
| rbug_connection.c | 35 enum rbug_opcode opcode; member in struct:rbug_connection
90 data->opcode = 0;
134 rbug_connection_send_start(struct rbug_connection *c, enum rbug_opcode opcode, uint32_t length)
136 c->opcode = opcode;
160 if (c->opcode < 0)
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/tgsi/ |
| tgsi_transform.c | 168 enum tgsi_opcode opcode = fullinst->Instruction.Opcode; local
189 if ((opcode == TGSI_OPCODE_END || opcode == TGSI_OPCODE_RET) &&
191 if (opcode == TGSI_OPCODE_RET && cond_stack != 0) {
203 switch (opcode) {
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sb/ |
| sb_bc_decoder.cpp | 41 unsigned opcode = ctx.is_egcm() ? local
45 bc.set_op(r600_isa_cf_by_opcode(ctx.isa, opcode, 0));
334 if (((r600_alu_op_table[k].opcode[1] >> 8) & 0xff) == iw1.get_LDS_OP()) {
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sfn/ |
| sfn_instruction_gds.cpp | 127 RatInstruction::ERatOp RatInstruction::opcode(nir_intrinsic_op opcode) function in class:r600::RatInstruction
129 switch (opcode) {
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/ |
| brw_structs.h | 48 unsigned opcode:16; member in struct:brw_urb_fence::__anon2574
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/rbug/ |
| rbug_connection.c | 35 enum rbug_opcode opcode; member in struct:rbug_connection
90 data->opcode = 0;
134 rbug_connection_send_start(struct rbug_connection *c, enum rbug_opcode opcode, uint32_t length)
136 c->opcode = opcode;
160 if (c->opcode < 0)
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/tgsi/ |
| tgsi_transform.c | 168 enum tgsi_opcode opcode = fullinst->Instruction.Opcode; local
189 if ((opcode == TGSI_OPCODE_END || opcode == TGSI_OPCODE_RET) &&
191 if (opcode == TGSI_OPCODE_RET && cond_stack != 0) {
203 switch (opcode) {
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/sb/ |
| sb_bc_decoder.cpp | 41 unsigned opcode = ctx.is_egcm() ? local
45 bc.set_op(r600_isa_cf_by_opcode(ctx.isa, opcode, 0));
334 if (((r600_alu_op_table[k].opcode[1] >> 8) & 0xff) == iw1.get_LDS_OP()) {
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| si_build_pm4.h | 110 unsigned opcode = PKT3_SET_UCONFIG_REG_INDEX; local
113 opcode = PKT3_SET_UCONFIG_REG;
114 radeon_emit(cs, PKT3(opcode, 1, 0));
|
| si_pm4.c | 29 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
31 state->last_opcode = opcode;
52 unsigned opcode; local
55 opcode = PKT3_SET_CONFIG_REG;
59 opcode = PKT3_SET_SH_REG;
63 opcode = PKT3_SET_CONTEXT_REG;
67 opcode = PKT3_SET_UCONFIG_REG;
77 if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
78 si_pm4_cmd_begin(state, opcode);
|
| /xsrc/external/mit/MesaLib.old/dist/src/intel/common/ |
| gen_disasm.c | 36 is_send(uint32_t opcode)
38 return (opcode == BRW_OPCODE_SEND ||
39 opcode == BRW_OPCODE_SENDC ||
40 opcode == BRW_OPCODE_SENDS ||
41 opcode == BRW_OPCODE_SENDSC );
51 /* This loop exits when send-with-EOT or when opcode is 0 */
62 uint32_t opcode = brw_inst_opcode(devinfo, insn); local
63 if (opcode == 0 || (is_send(opcode) && brw_inst_eot(devinfo, insn))) {
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/ |
| brw_structs.h | 48 unsigned opcode:16; member in struct:brw_urb_fence::__anon4897
|
| /xsrc/external/mit/MesaLib/dist/src/compiler/nir/ |
| nir_lower_bool_to_bitsize.c | 150 nir_op opcode = alu->op; local
151 switch (opcode) {
167 opcode = bit_size == 8 ? nir_op_f2b8 :
172 opcode = bit_size == 8 ? nir_op_i2b8 :
178 opcode = nir_op_mov;
183 opcode = nir_op_i2i32;
187 opcode = bit_size == 8 ? nir_op_flt8 :
192 opcode = bit_size == 8 ? nir_op_fge8 :
197 opcode = bit_size == 8 ? nir_op_feq8 :
202 opcode = bit_size == 8 ? nir_op_fneu8
[all...] |
