Searched defs:pll (Results 1 - 23 of 23) sorted by relevance

/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dradeon_mm_i2c.c367 RADEONPLLPtr pll = &(info->pll); local in function:RADEONInitI2C
H A Dradeon_pm.c51 RADEONPLLPtr pll = &info->pll; local in function:calc_eng_mem_clock
H A Dradeon_crtc.c146 RADEONComputePLL_old(RADEONPLLPtr pll, argument
323 calc_fb_div(RADEONPLLPtr pll,unsigned long freq,int flags,int post_div,int ref_div,int * fb_div,int * fb_div_frac) argument
352 calc_fb_ref_div(RADEONPLLPtr pll,unsigned long freq,int flags,int post_div,int * fb_div,int * fb_div_frac,int * ref_div) argument
382 RADEONComputePLL_new(RADEONPLLPtr pll,unsigned long freq,uint32_t * chosen_dot_clock_freq,uint32_t * chosen_feedback_div,uint32_t * chosen_frac_feedback_div,uint32_t * chosen_reference_div,uint32_t * chosen_post_div,int flags) argument
465 RADEONComputePLL(xf86CrtcPtr crtc,RADEONPLLPtr pll,unsigned long freq,uint32_t * chosen_dot_clock_freq,uint32_t * chosen_feedback_div,uint32_t * chosen_frac_feedback_div,uint32_t * chosen_reference_div,uint32_t * chosen_post_div,int flags) argument
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H A Dradeon_tv.c618 RADEONPLLPtr pll = &info->pll; local in function:RADEONInitTVRestarts
741 RADEONPLLPtr pll = &info->pll; local in function:RADEONInitTVRegisters
1083 RADEONPLLPtr pll = &info->pll; local in function:RADEONAdjustCrtcRegistersForTV
1124 RADEONPLLPtr pll = &info->pll; local in function:RADEONAdjustPLLRegistersForTV
1187 RADEONPLLPtr pll = &info->pll; local in function:RADEONAdjustCrtc2RegistersForTV
1228 RADEONPLLPtr pll = &info->pll; local in function:RADEONAdjustPLL2RegistersForTV
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H A Dlegacy_crtc.c1188 RADEONInitPLLRegisters(xf86CrtcPtr crtc,RADEONSavePtr save,RADEONPLLPtr pll,DisplayModePtr mode,int flags) argument
1279 RADEONInitPLL2Registers(xf86CrtcPtr crtc,RADEONSavePtr save,RADEONPLLPtr pll,DisplayModePtr mode,int flags) argument
H A Dradeon_bios.c986 RADEONPLLPtr pll = &info->pll; local in function:RADEONGetClockInfoFromBIOS
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H A Dradeon_atombios.c2267 RADEONPLLPtr pll = &info->pll; local in function:RADEONGetATOMClockInfo
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H A Dradeon_driver.c1010 RADEONPLLPtr pll = &info->pll; local in function:RADEONProbePLLParameters
1215 RADEONPLLPtr pll = &info->pll; local in function:RADEONGetClockInfo
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H A Dradeon_video.c1377 RADEONPLLPtr pll = &(info->pll); local in function:RADEONSetupTheatre
H A Dradeon_probe.h456 uint32_t pll[2][15]; member in struct:dce4_state
484 struct avivo_pll_state pll[2]; member in struct:avivo_state
H A Dradeon.h856 RADEONPLLRec pll; member in struct:__anonb194aea90e08
/xsrc/external/mit/xf86-video-siliconmotion/dist/src/
H A Dsmi_501.c239 int32_t pll; local in function:SMI501_WriteMode_common
286 int32_t pll; local in function:SMI501_WriteMode_lcd
325 int32_t pll; local in function:SMI501_WriteMode_crt
637 SMI501_SetClock(SMIPtr pSmi,int32_t port,int32_t pll,int32_t value) argument
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H A Dsmi_501.h448 int32_t pll : bits( 4, 5); member in struct:_MSOCRegRec::__anone5fa72d7100a::__anone5fa72d71108
/xsrc/external/mit/xf86-video-openchrome/dist/src/
H A Dvia_outputs.c794 union pllparams pll; local in function:ViaSetDotclock
/xsrc/external/mit/xf86-video-openchrome/dist/tools/
H A Dregisters.c858 enum pll { enum
866 static void get_vck_clock(enum pll pll, unsigned int f_ref_khz) argument
/xsrc/external/mit/xf86-video-r128/dist/src/
H A Dr128_crtc.c347 R128InitPLLRegisters(xf86CrtcPtr crtc,R128SavePtr save,R128PLLPtr pll,double dot_clock) argument
403 R128InitPLL2Registers(xf86CrtcPtr crtc,R128SavePtr save,R128PLLPtr pll,double dot_clock) argument
640 R128InitDDARegisters(xf86CrtcPtr crtc,R128SavePtr save,R128PLLPtr pll,DisplayModePtr mode) argument
716 R128InitDDA2Registers(xf86CrtcPtr crtc,R128SavePtr save,R128PLLPtr pll,DisplayModePtr mode) argument
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H A Dr128_driver.c605 R128PLLPtr pll = &info->pll; local in function:R128GetPLLParameters
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H A Dr128.h332 R128PLLRec pll; member in struct:__anona5d7874c0508
/xsrc/external/mit/xf86-video-nsc/dist/src/gfx/
H A Dvid_1200.c421 unsigned long value, pll; local in function:sc1200_set_clock_frequency
/xsrc/external/mit/xf86-video-nv/dist/src/
H A Dnv_hw.c126 unsigned int pll, N, M, MB, NB, P; local in function:nvGetClocks
684 unsigned int M, N, P, pll, MClk, NVClk, memctrl; local in function:nForceUpdateArbitrationSettings
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H A Driva_hw.c528 unsigned int M, N, P, pll, MClk; local in function:nv3UpdateArbitrationSettings
H A Dnv_type.h50 U032 pll; member in struct:_riva_hw_state
/xsrc/external/mit/xf86-video-geode/dist/src/gfx/
H A Dvid_1200.c262 unsigned long value, pll; local in function:sc1200_set_clock_frequency

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