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    Searched defs:regval (Results 1 - 25 of 30) sorted by relevancy

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  /src/sys/arch/netwinder/pci/
pci_machdep.c 17 pcireg_t regval; local in function:netwinder_pci_attach_hook
71 regval = pci_conf_read(pba->pba_pc, tag, 0x40);
72 regval &= 0xff00ff00;
73 regval |= 0x00000022;
74 pci_conf_write(pba->pba_pc, tag, 0x40, regval);
76 regval = pci_conf_read(pba->pba_pc, tag, 0x80);
77 regval &= 0x0000ff00;
78 regval |= 0xe0010002;
79 pci_conf_write(pba->pba_pc, tag, 0x80, regval);
91 regval = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG)
    [all...]
  /src/sys/arch/mips/sibyte/pci/
sbpcihb.c 81 uint64_t regval; local in function:sbpcihb_attach
85 regval = mips3_ld((void *)MIPS_PHYS_TO_KSEG0(A_SCD_SYSTEM_CFG));
86 host = (regval & M_SYS_PCI_HOST) != 0;
sbbrz.c 173 uint64_t regval; local in function:sbbrz_attach
177 regval = mips3_ld((register_t)MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG));
178 host = (regval & M_SYS_PCI_HOST) != 0;
sbbrz_pci.c 142 uint64_t regval; local in function:sbbrz_pci_bus_maxdevs
150 regval = mips3_ld((register_t)MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG));
151 host = (regval & M_SYS_PCI_HOST) != 0;
  /src/sys/dev/ic/
vga_common.c 50 u_int8_t regval; local in function:vga_common_probe
62 regval = bus_space_read_1(iot, ioh_vga, VGA_MISC_DATAR);
63 mono = !(regval & 1);
90 regval = bus_space_read_1(iot, ioh_vga, VGA_ATC_DATAR);
92 bus_space_write_1(iot, ioh_vga, VGA_ATC_DATAW, regval ^ 0x0f);
95 if (bus_space_read_1(iot, ioh_vga, VGA_ATC_DATAR) != (regval ^ 0x0f))
98 bus_space_write_1(iot, ioh_vga, VGA_ATC_DATAW, regval);
bt485.c 196 u_int8_t regval; local in function:bt485_init
209 regval = data->ramdac_rd(data->cookie, BT485_REG_COMMAND_0);
210 regval |= 0x80;
215 regval |= 0x02;
216 data->ramdac_wr(data->cookie, BT485_REG_COMMAND_0, regval);
222 regval = data->ramdac_rd(data->cookie, BT485_REG_COMMAND_2);
223 regval &= ~0x03;
224 regval |= 0x24;
225 data->ramdac_wr(data->cookie, BT485_REG_COMMAND_2, regval);
228 regval = bt485_rd_i(data, BT485_IREG_COMMAND_3)
481 u_int8_t regval; local in function:bt485_update
    [all...]
nslm7x.c 2367 uint8_t regval, banksel; local in function:wb_temp_diode_type
2373 regval = (*sc->lm_readreg)(sc, WB_BANK0_VBAT);
2374 regval |= 0x0e;
2375 (*sc->lm_writereg)(sc, WB_BANK0_VBAT, regval);
2376 regval = (*sc->lm_readreg)(sc, WB_BANK0_RESVD1);
2377 regval |= 0x70;
2384 regval = (*sc->lm_readreg)(sc, WB_BANK0_VBAT);
2385 regval |= 0xe;
2386 (*sc->lm_writereg)(sc, WB_BANK0_VBAT, regval);
2387 regval = (*sc->lm_readreg)(sc, WB_BANK0_RESVD1)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_opp.c 389 uint32_t regval = enable ? 1 : 0; local in function:opp1_pipe_clock_control
391 REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval);
amdgpu_dcn10_dpp_cm.c 98 const uint16_t *regval,
104 if (regval == NULL || select == GAMUT_REMAP_BYPASS) {
135 regval,
145 regval,
155 regval,
191 const uint16_t *regval)
197 if (regval == NULL) {
237 regval,
249 const uint16_t *regval = NULL; local in function:dpp1_cm_set_output_csc_default
252 regval = find_color_matrix(colorspace, &arr_size)
434 const uint16_t *regval = NULL; local in function:dpp1_program_input_csc
    [all...]
amdgpu_dcn10_optc.c 598 uint32_t regval = 0; local in function:optc1_lock
600 regval = REG_READ(OTG_CONTROL);
603 if ((regval & 0x1) == 0x0)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
amdgpu_hw_ddc.c 80 uint32_t regval; local in function:set_config
92 regval = REG_GET_3(gpio.MASK_reg,
106 REG_SET_2(gpio.MASK_reg, regval,
124 REG_SET(gpio.MASK_reg, regval,
133 REG_SET(gpio.MASK_reg, regval,
169 REG_SET(gpio.MASK_reg, regval,
  /src/sys/arch/hpcmips/dev/
mq200.c 93 unsigned long regval; local in function:mq200_probe
100 regval = bus_space_read_4(iot, ioh, MQ200_PC00R);
102 regval & 0xffff, (regval >> 16) & 0xffff);
103 if (regval != ((MQ200_PRODUCT_ID << 16) | MQ200_VENDOR_ID))
112 unsigned long regval; local in function:mq200_attach
128 regval = mq200_read(sc, MQ200_PC08R);
129 printf("MQ200 Rev.%02lx video controller", regval & 0xff);
ite8181.c 225 unsigned long regval; local in function:ite8181_probe
232 regval = ite8181_config_read_4(iot, ioh, ITE8181_ID);
234 regval & 0xffff, (regval >> 16) & 0xffff));
235 if (regval != ((ITE8181_PRODUCT_ID << 16) | ITE8181_VENDER_ID))
244 unsigned long regval; local in function:ite8181_attach
254 regval = ite8181_config_read_4(sc->sc_iot, sc->sc_ioh, ITE8181_CLASS);
255 printf("ITE8181 Rev.%02lx", regval & ITE8181_REV_MASK);
  /src/sys/dev/i2c/
mt2131.c 131 uint8_t regval; local in function:mt2131_tune_dtv
166 regval = (fr - 27501) / 55000;
168 if(regval > 0x13)
169 regval = 0x13;
171 rv = mt2131_write(sc, UPC_1, regval);
181 rv = mt2131_read(sc, 0x08, &regval);
185 if (( regval & 0x88 ) == 0x88 ) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_hw_sequencer.c 78 uint16_t regval[12]; member in struct:out_csc_color_matrix_type
221 val = output_csc_matrix[i].regval;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_opp_csc_v.c 137 tbl_entry->regval[0],
143 tbl_entry->regval[1],
155 tbl_entry->regval[2],
161 tbl_entry->regval[3],
173 tbl_entry->regval[4],
179 tbl_entry->regval[5],
191 tbl_entry->regval[6],
197 tbl_entry->regval[7],
209 tbl_entry->regval[8],
215 tbl_entry->regval[9]
513 uint32_t regval[12]; member in struct:input_csc_matrix
541 const uint32_t *regval = NULL; local in function:program_input_csc
    [all...]
amdgpu_dce110_timing_generator_v.c 599 uint32_t regval; local in function:dce110_timing_generator_v_set_early_control
602 regval = dm_read_reg(tg->ctx, address);
603 set_reg_field_value(regval, early_cntl,
605 dm_write_reg(tg->ctx, address, regval);
amdgpu_dce110_timing_generator.c 114 uint32_t regval; local in function:dce110_timing_generator_set_early_control
118 regval = dm_read_reg(tg->ctx, address);
119 set_reg_field_value(regval, early_cntl,
121 dm_write_reg(tg->ctx, address, regval);
264 uint32_t regval; local in function:program_horz_count_by_2
267 regval = dm_read_reg(tg->ctx,
270 set_reg_field_value(regval, 0, CRTC_COUNT_CONTROL,
274 set_reg_field_value(regval, 1, CRTC_COUNT_CONTROL,
278 CRTC_REG(mmCRTC_COUNT_CONTROL), regval);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_mpc.c 140 const uint16_t *regval,
152 if (regval == NULL) {
185 regval,
201 const uint16_t *regval = NULL; local in function:mpc2_set_ocsc_default
208 regval = find_color_matrix(color_space, &arr_size);
210 if (regval == NULL) {
244 regval,
amdgpu_dcn20_dpp_cm.c 168 const uint16_t *regval,
174 if (regval == NULL || select == DCN2_GAMUT_REMAP_BYPASS) {
209 regval,
251 const uint16_t *regval = NULL; local in function:dpp2_program_input_csc
264 regval = dpp_input_csc_matrix[i].regval;
268 if (regval == NULL) {
273 regval = tbl_entry->regval;
308 regval,
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
dpp.h 49 uint16_t regval[12]; member in struct:dpp_input_csc_matrix
161 const uint16_t *regval);
  /src/sys/dev/pci/ixgbe/
ixgbe_82598.c 262 u32 regval; local in function:ixgbe_start_hw_82598
275 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
276 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
277 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
282 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
283 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
285 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
1369 u32 regval; local in function:ixgbe_enable_relaxed_ordering_82598
1377 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1378 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN
    [all...]
  /src/sys/dev/usb/
ustir.c 454 uint8_t regval; local in function:ustir_periodic
460 &regval);
468 (unsigned int)regval));
470 !(regval & STIR_RSTATUS_FFDIR))
473 if (regval & STIR_RSTATUS_FFOVER) {
  /src/sys/arch/arm/samsung/
exynos_soc.c 304 uint32_t regval; local in function:exynos_get_cpufreq
307 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_apll_bsh,
309 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval);
319 uint32_t regval; local in function:exynos_set_cpufreq
327 regval = __SHIFTIN(M, PLL_CON0_M) |
332 regval |= PLL_CON0_ENABLE;
334 regval);
409 regval = bus_space_read_4(&armv7_generic_bs_tag, exynos_cmu_bsh, reg); \
410 freq = PLL_FREQ(EXYNOS_F_IN_FREQ, regval); \
418 uint32_t regval; local in function:exynos_dump_clocks
676 uint32_t en_mask, regval; local in function:exynos_usb2_set_isolation
    [all...]
  /src/sys/arch/riscv/starfive/
jh7100_pinctrl.c 132 const uint32_t regval = val << shift; local in function:jh7100_padctl_rmw
138 reg |= regval;

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