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    Searched defs:tiling_flags (Results 1 - 23 of 23) sorted by relevancy

  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/
radeon_common_context.c 513 uint32_t tiling_flags = 0, pitch = 0; local
529 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch);
538 if (tiling_flags & RADEON_TILING_MACRO)
540 if (tiling_flags & RADEON_TILING_MICRO)
  /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/
radv_amdgpu_bo.c 659 uint32_t tiling_flags = 0; local
662 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode);
665 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
667 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */
669 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
671 tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->u.legacy.pipe_config);
672 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw));
673 tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->u.legacy.bankh));
675 tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, radv_eg_tile_split_rev(md->u.legacy.tile_split));
676 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea))
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/
radeon_common_context.c 512 uint32_t tiling_flags = 0, pitch = 0; local
528 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch);
537 if (tiling_flags & RADEON_TILING_MACRO)
539 if (tiling_flags & RADEON_TILING_MICRO)
  /xsrc/external/mit/xf86-video-ati-kms/dist/src/
radeon_bo_helper.c 112 int width, int height, int cpp, uint32_t tiling_flags,
133 tiling_flags &= ~RADEON_TILING_MACRO;
144 if ((tiling_flags & RADEON_TILING_MACRO)) {
147 } else if ((tiling_flags & RADEON_TILING_MICRO)) {
154 surface->bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) &
156 surface->bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) &
158 surface->tile_split = eg_tile_split_opp((tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) &
162 (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) &
165 surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) &
404 priv->tiling_flags = args.tiling_flags
517 uint32_t tiling_flags; local
    [all...]
radeon_present.c 203 uint32_t tiling_flags = radeon_get_pixmap_tiling_flags(pixmap); local
208 if ((tiling_flags & RADEON_TILING_MACRO) &&
210 tiling_flags &= ~RADEON_TILING_MICRO;
212 return tiling_flags;
radeon_kms.c 2762 uint32_t tiling_flags = 0; local
2820 &tiling_flags);
2832 tiling_flags |= RADEON_TILING_SWAP_32BIT;
2835 tiling_flags |= RADEON_TILING_SWAP_16BIT;
2839 info->r600_shadow_fb && tiling_flags)
2840 tiling_flags |= RADEON_TILING_SURFACE;
2842 if (tiling_flags)
2843 radeon_bo_set_tiling(info->front_buffer->bo.radeon, tiling_flags, pitch);
drmmode_display.c 2422 uint32_t tiling_flags; local
2460 &tiling_flags);
2470 tiling_flags |= RADEON_TILING_SWAP_32BIT;
2473 tiling_flags |= RADEON_TILING_SWAP_16BIT;
2477 info->r600_shadow_fb && tiling_flags)
2478 tiling_flags |= RADEON_TILING_SURFACE;
2480 if (tiling_flags)
2481 radeon_bo_set_tiling(info->front_buffer->bo.radeon, tiling_flags, pitch);
radeon.h 318 uint32_t tiling_flags; member in struct:radeon_pixmap
343 uint32_t tiling_flags; member in struct:radeon_exa_pixmap_priv
384 uint32_t tiling_flags; member in struct:r600_accel_object
654 int width, int height, int cpp, uint32_t tiling_flags,
783 radeon_bo_get_tiling(bo->bo.radeon, &driver_priv->tiling_flags,
786 driver_priv->tiling_flags = 0;
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
radv_amdgpu_bo.c 913 uint64_t tiling_flags = 0; local
916 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode);
917 tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, md->u.gfx9.dcc_offset_256b);
918 tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, md->u.gfx9.dcc_pitch_max);
919 tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, md->u.gfx9.dcc_independent_64b_blocks);
920 tiling_flags |=
922 tiling_flags |=
924 tiling_flags |= AMDGPU_TILING_SET(SCANOUT, md->u.gfx9.scanout);
927 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
929 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 *
    [all...]
  /xsrc/external/mit/xf86-video-ati/dist/src/
radeon_kms.c 1233 uint32_t tiling_flags = 0; local
1251 tiling_flags |= RADEON_TILING_MACRO;
1253 tiling_flags |= RADEON_TILING_MICRO;
1256 tiling_flags |= RADEON_TILING_MACRO;
1258 pitch = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp;
1259 screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch;
1260 base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags);
1281 if (tiling_flags & RADEON_TILING_MICRO) {
1285 if (tiling_flags & RADEON_TILING_MACRO) {
1302 tiling_flags = 0
    [all...]
drmmode_display.c 246 uint32_t tiling_flags = 0; local
269 tiling_flags |= RADEON_TILING_MACRO;
271 tiling_flags |= RADEON_TILING_MICRO;
274 tiling_flags |= RADEON_TILING_MACRO;
278 drmmode_get_pitch_align(pScrn, info->CurrentLayout.pixel_bytes, tiling_flags)) *
284 tiling_flags, info->front_bo, &info->front_surface);
333 uint32_t tiling_flags = 0; local
338 tiling_flags |= RADEON_TILING_MICRO;
340 tiling_flags |= RADEON_TILING_MACRO;
343 pitch = RADEON_ALIGN(pScrn->displayWidth, drmmode_get_pitch_align(pScrn, info->CurrentLayout.pixel_bytes, tiling_flags)) *
1269 uint32_t tiling_flags = 0, base_align; local
1794 uint32_t tiling_flags = 0; local
    [all...]
radeon.h 450 uint32_t tiling_flags; member in struct:radeon_exa_pixmap_priv
632 uint32_t tiling_flags; member in struct:r600_accel_object
radeon_drm.h 823 uint32_t tiling_flags; member in struct:drm_radeon_gem_set_tiling
829 uint32_t tiling_flags; member in struct:drm_radeon_gem_get_tiling
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/
iris_resource.c 568 isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK; local
573 tiling_flags = 1 << res->mod_info->tiling;
584 tiling_flags = ISL_TILING_Y0_BIT;
587 tiling_flags = ISL_TILING_W_BIT;
592 tiling_flags = ISL_TILING_LINEAR_BIT;
598 tiling_flags = ISL_TILING_LINEAR_BIT;
636 .tiling_flags = tiling_flags);
810 .tiling_flags = 1 << res->mod_info->tiling);
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/amdgpu/drm/
amdgpu_bo.c 1218 uint64_t tiling_flags; local
1227 tiling_flags = info.metadata.tiling_info;
1230 md->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
1232 md->u.gfx9.dcc_offset_256B = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
1233 md->u.gfx9.dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX);
1234 md->u.gfx9.dcc_independent_64B = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_64B);
1239 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */
1241 else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */
1244 md->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1245 md->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH)
1262 uint64_t tiling_flags = 0; local
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/intel/isl/
isl.c 380 isl_tiling_flags_t tiling_flags = info->tiling_flags; local
385 assert(tiling_flags == ISL_TILING_HIZ_BIT);
393 assert(tiling_flags == ISL_TILING_CCS_BIT);
399 isl_gen6_filter_tiling(dev, info, &tiling_flags);
401 isl_gen4_filter_tiling(dev, info, &tiling_flags);
406 if (tiling_flags & (1u << (__tiling))) { \
1673 .tiling_flags = ISL_TILING_HIZ_BIT);
1721 .tiling_flags = ISL_TILING_Y0_BIT);
1808 .tiling_flags = ISL_TILING_CCS_BIT)
    [all...]
isl.h 1155 isl_tiling_flags_t tiling_flags; member in struct:isl_surf_init_info
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
crocus_resource.c 181 isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK; local
185 tiling_flags &= ~ISL_TILING_Y0_BIT;
190 tiling_flags = 1 << res->mod_info->tiling;
195 tiling_flags = 1 << res->mod_info->tiling;
200 tiling_flags = ISL_TILING_LINEAR_BIT;
202 tiling_flags = screen->devinfo.has_tiling_uapi ?
225 tiling_flags = ISL_TILING_W_BIT;
251 .tiling_flags = tiling_flags
  /xsrc/external/mit/MesaLib/dist/src/intel/isl/
isl.c 591 isl_tiling_flags_t tiling_flags = info->tiling_flags; local
596 assert(tiling_flags == ISL_TILING_HIZ_BIT);
597 *tiling = isl_tiling_flag_to_enum(tiling_flags);
605 tiling_flags == ISL_TILING_CCS_BIT;
607 tiling_flags == ISL_TILING_GFX12_CCS_BIT;
609 *tiling = isl_tiling_flag_to_enum(tiling_flags);
614 isl_gfx125_filter_tiling(dev, info, &tiling_flags);
616 isl_gfx6_filter_tiling(dev, info, &tiling_flags);
618 isl_gfx4_filter_tiling(dev, info, &tiling_flags);
    [all...]
isl.h 1447 isl_tiling_flags_t tiling_flags; member in struct:isl_surf_init_info
  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
brw_mipmap_tree.c 352 unsigned num_samples, isl_tiling_flags_t tiling_flags,
390 .tiling_flags = tiling_flags,
406 init_info.tiling_flags = 1u << ISL_TILING_LINEAR;
410 init_info.tiling_flags = 1u << ISL_TILING_X;
484 isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK; local
488 tiling_flags &= ~ISL_TILING_Y0_BIT;
501 tiling_flags, mt_surf_usage(mt_fmt),
511 num_samples, tiling_flags,
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
intel_mipmap_tree.c 552 unsigned num_samples, isl_tiling_flags_t tiling_flags,
590 .tiling_flags = tiling_flags,
606 init_info.tiling_flags = 1u << ISL_TILING_LINEAR;
610 init_info.tiling_flags = 1u << ISL_TILING_X;
684 isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK; local
688 tiling_flags &= ~ISL_TILING_Y0_BIT;
701 tiling_flags, mt_surf_usage(mt_fmt),
711 num_samples, tiling_flags,
  /xsrc/external/mit/libdrm/dist/include/drm/
radeon_drm.h 859 __u32 tiling_flags; member in struct:drm_radeon_gem_set_tiling
865 __u32 tiling_flags; member in struct:drm_radeon_gem_get_tiling

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