| /xsrc/external/mit/MesaLib.old/dist/src/intel/dev/ |
| gen_device_info.h | 99 * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
100 * limits come from the "Number of URB Entries" field in the
200 * Hardware default URB size.
205 * Look up "URB Size" in the "Device Attributes" page, and take the
207 * urb.size = URB Size (kbytes) / slice count
212 * The minimum number of URB entries. See the 3DSTATE_URB_<XS> docs.
217 * The maximum number of URB entries. See the 3DSTATE_URB_<XS> docs.
220 } urb; member in struct:gen_device_info
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| /xsrc/external/mit/MesaLib/dist/src/intel/dev/ |
| intel_device_info.h | 116 * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
117 * limits come from the "Number of URB Entries" field in the
265 * Fixed size of the URB.
270 * On most Gfx7+ platforms, the URB is a section of the L3 cache,
277 * The minimum number of URB entries. See the 3DSTATE_URB_<XS> docs.
282 * The maximum number of URB entries. See the 3DSTATE_URB_<XS> docs.
285 } urb; member in struct:intel_device_info
287 /* Maximum size in Kb that can be allocated to constants in the URB, this
|
| /xsrc/external/mit/xf86-video-intel/dist/src/sna/ |
| gen6_render.c | 82 } urb; member in struct:gt_info
91 .urb = { 32, 256, 256 },
100 .urb = { 64, 256, 256 },
479 (sna->render_state.gen6.info->urb.max_vs_entries << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
|
| gen7_render.c | 91 } urb; member in struct:gt_info
101 .urb = { 128, 64, 64, 8 },
110 .urb = { 128, 512, 192, 8 },
120 .urb = { 256, 704, 320, 8 },
130 .urb = { 128, 512, 192, 8 },
141 .urb = { 128, 64, 64, 8 },
152 .urb = { 128, 640, 256, 8 },
164 .urb = { 256, 1664, 640, 8 },
176 .urb = { 512, 3328, 1280, 16 },
540 OUT_BATCH(sna->render_state.gen7.info->urb.push_ps_size)
[all...] |
| gen8_render.c | 251 } urb; member in struct:gt_info
256 .urb = { .max_vs_entries = 960 },
266 .urb = { .max_vs_entries = 640 },
531 OUT_BATCH(sna->render_state.gen8.info->urb.max_vs_entries << URB_ENTRY_NUMBER_SHIFT |
591 OUT_BATCH(1 << 16 | 1 << 21); /* urb write to SBE */
|
| gen9_render.c | 267 } urb; member in struct:gt_info
272 .urb = { .max_vs_entries = 240 },
277 .urb = { .max_vs_entries = 960 },
282 .urb = { .max_vs_entries = 320 },
287 .urb = { .max_vs_entries = 960 },
292 .urb = { .max_vs_entries = 320 },
297 .urb = { .max_vs_entries = 960 },
582 OUT_BATCH(sna->render_state.gen9.info->urb.max_vs_entries << URB_ENTRY_NUMBER_SHIFT |
648 OUT_BATCH(1 << 16 | 1 << 21); /* urb write to SBE */
|
| gen4_render.h | 2410 struct gen4_urb_immediate urb; member in union:gen4_instruction::__anon7181
|
| gen5_render.h | 2490 struct gen5_urb_immediate urb; member in union:gen5_instruction::__anon7367
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| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/ |
| gen6_render.c | 82 } urb; member in struct:gt_info
91 .urb = { 32, 256, 256 },
100 .urb = { 64, 256, 256 },
445 (sna->render_state.gen6.info->urb.max_vs_entries << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
|
| gen7_render.c | 93 } urb; member in struct:gt_info
103 .urb = { 128, 64, 64, 8 },
112 .urb = { 128, 512, 192, 8 },
122 .urb = { 256, 704, 320, 8 },
132 .urb = { 128, 512, 192, 8 },
143 .urb = { 128, 64, 64, 8 },
154 .urb = { 128, 640, 256, 8 },
166 .urb = { 256, 1664, 640, 8 },
178 .urb = { 512, 3328, 1280, 16 },
503 OUT_BATCH(sna->render_state.gen7.info->urb.push_ps_size)
[all...] |
| gen4_render.h | 2410 struct gen4_urb_immediate urb; member in union:gen4_instruction::__anon8051
|
| gen5_render.h | 2490 struct gen5_urb_immediate urb; member in union:gen5_instruction::__anon8237
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/ |
| crocus_context.h | 538 /* Track last VS URB entry size */
687 uint32_t vsize; /* vertex size plus header in urb registers */
688 uint32_t gsize; /* GS output size in urb registers */
689 uint32_t hsize; /* Tessellation control output size in urb registers */
690 uint32_t dsize; /* Tessellation evaluation output size in urb registers */
691 uint32_t csize; /* constant buffer size in urb registers */
692 uint32_t sfsize; /* setup data size in urb registers */
712 * URB size in the current configuration. The units this is expressed
713 * in are somewhat inconsistent, see intel_device_info::urb::size.
715 * FINISHME: Represent the URB size consistently in KB on all platforms
728 } urb; member in struct:crocus_context
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/ |
| iris_context.h | 670 } urb; member in struct:iris_context::__anon1234
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/ |
| brw_context.h | 61 * URB - uniform resource buffer. A mid-sized buffer which is
65 * CURBE - constant URB entry. An urb region (entry) used to hold
69 * VUE - vertex URB entry. An urb entry holding a vertex and usually
73 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
78 * urb) of the thread are preloaded to this area before the thread is
85 * MRF registers. All program output is via these messages. URB
86 * entries are populated by sending a message to the shared URB
1050 } urb; member in struct:brw_context
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/ |
| brw_context.h | 59 * URB - uniform resource buffer. A mid-sized buffer which is
63 * CURBE - constant URB entry. An urb region (entry) used to hold
67 * VUE - vertex URB entry. An urb entry holding a vertex and usually
71 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
76 * urb) of the thread are preloaded to this area before the thread is
83 * MRF registers. All program output is via these messages. URB
84 * entries are populated by sending a message to the shared URB
1030 } urb; member in struct:brw_context
[all...] |
| /xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/ |
| brw_eu.h | 937 } urb; member in union:brw_instruction::__anon7056
|
| /xsrc/external/mit/xf86-video-intel/dist/src/uxa/ |
| brw_structs.h | 1347 struct brw_urb_immediate urb; member in union:brw_instruction::__anon7617
|
| /xsrc/external/mit/xf86-video-intel/dist/xvmc/ |
| brw_structs.h | 1347 struct brw_urb_immediate urb; member in union:brw_instruction::__anon7784
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/ |
| brw_eu.h | 937 } urb; member in union:brw_instruction::__anon7926
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/ |
| brw_structs.h | 1347 struct brw_urb_immediate urb; member in union:brw_instruction::__anon8471
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/ |
| brw_structs.h | 1347 struct brw_urb_immediate urb; member in union:brw_instruction::__anon8633
|
| /xsrc/external/mit/xf86-video-intel-old/dist/src/ |
| brw_structs.h | 1342 struct brw_urb_immediate urb; member in union:brw_instruction::__anon8824
|
| /xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/ |
| anv_private.h | 1525 * Header for Vertex URB Entry (VUE)
2755 } urb; member in struct:anv_pipeline
|
