| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvif/ |
| cl0046.h | 25 __u16 vline; member in struct:nv04_disp_scanoutpos_v0
|
| cl5070.h | 24 __u16 vline; member in struct:nv50_disp_scanoutpos_v0
|
| /src/lib/libcurses/ |
| line.c | 115 * vline --
119 vline(chtype ch, int count) function in typeref:typename:int
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 92 uint32_t vline; member in struct:__anon55e5877b0108
98 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
118 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
123 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
3253 case 1: /* vline */
3254 if (disp_int & interrupt_status_offsets[crtc].vline)
3259 DRM_DEBUG("IH: D%d vline\n", crtc + 1)
[all...] |
| amdgpu_dce_v11_0.c | 94 uint32_t vline; member in struct:__anon55f79ffc0108
100 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
105 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
110 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
115 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
120 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
125 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
3380 case 1: /* vline */
3381 if (disp_int & interrupt_status_offsets[crtc].vline)
3386 DRM_DEBUG("IH: D%d vline\n", crtc + 1)
[all...] |
| amdgpu_dce_v6_0.c | 95 uint32_t vline; member in struct:__anonadb87c700108
101 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
106 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
111 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
116 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
121 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
126 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
2974 case 1: /* vline */
2975 if (disp_int & interrupt_status_offsets[crtc].vline)
2980 DRM_DEBUG("IH: D%d vline\n", crtc + 1)
[all...] |
| amdgpu_dce_v8_0.c | 92 uint32_t vline; member in struct:__anonaddcad720108
98 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
118 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
123 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
3064 case 1: /* vline */
3065 if (disp_int & interrupt_status_offsets[crtc].vline)
3070 DRM_DEBUG("IH: D%d vline\n", crtc + 1)
[all...] |
