| /src/lib/libcurses/ |
| line.c | 115 * vline --
119 vline(chtype ch, int count) function
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvif/ |
| cl0046.h | 25 __u16 vline; member in struct:nv04_disp_scanoutpos_v0
|
| cl5070.h | 24 __u16 vline; member in struct:nv50_disp_scanoutpos_v0
|
| /src/external/gpl2/groff/dist/src/preproc/tbl/ |
| table.h | 101 char **vline; member in class:table
|
| main.cpp | 625 char **vline; member in struct:format
645 vline = new char*[nrows];
647 vline[i] = new char[ncolumns+1];
649 vline[i][j] = 0;
656 char **old_vline = vline;
657 vline = new char*[nrows + n];
659 vline[i] = old_vline[i];
662 vline[nrows + i] = new char[ncolumns + 1];
664 vline[nrows + i][j] = 0;
682 a_delete vline[i] local
685 a_delete vline; local
693 int vline; member in struct:input_entry_format
[all...] |
| table.cpp | 1205 vline(0), row_is_all_lines(0), left_separation(0), right_separation(0),
1223 a_delete vline[i]; local
1226 a_delete vline; local
1310 vline = new char*[allocated_rows];
1321 char **old_vline = vline;
1322 vline = new char*[allocated_rows];
1323 memcpy(vline, old_vline, sizeof(char*)*old_allocated_rows);
1333 vline[nrows] = new char[ncolumns+1];
1335 vline[nrows][i] = 0;
1610 vline[r][i] = v[i]
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 92 uint32_t vline; member in struct:__anon4294
98 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
118 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
123 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
3253 case 1: /* vline */
3254 if (disp_int & interrupt_status_offsets[crtc].vline)
3259 DRM_DEBUG("IH: D%d vline\n", crtc + 1)
[all...] |
| amdgpu_dce_v11_0.c | 94 uint32_t vline; member in struct:__anon4295
100 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
105 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
110 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
115 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
120 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
125 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
3380 case 1: /* vline */
3381 if (disp_int & interrupt_status_offsets[crtc].vline)
3386 DRM_DEBUG("IH: D%d vline\n", crtc + 1)
[all...] |
| amdgpu_dce_v6_0.c | 95 uint32_t vline; member in struct:__anon4296
101 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
106 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
111 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
116 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
121 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
126 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
2974 case 1: /* vline */
2975 if (disp_int & interrupt_status_offsets[crtc].vline)
2980 DRM_DEBUG("IH: D%d vline\n", crtc + 1)
[all...] |
| amdgpu_dce_v8_0.c | 92 uint32_t vline; member in struct:__anon4297
98 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
118 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
123 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
3064 case 1: /* vline */
3065 if (disp_int & interrupt_status_offsets[crtc].vline)
3070 DRM_DEBUG("IH: D%d vline\n", crtc + 1)
[all...] |
