| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_ih.c | 66 /* add 8 bytes for the rptr/wptr shadows and
159 /* add 8 bytes for the rptr/wptr shadows and
194 u32 wptr; local in function:amdgpu_ih_process
199 wptr = amdgpu_ih_get_wptr(adev, ih);
206 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr);
208 /* Order reading of wptr vs. reading of IH ring data */
211 while (ih->rptr != wptr && --count) {
219 /* make sure wptr hasn't changed while processing */
220 wptr = amdgpu_ih_get_wptr(adev, ih)
[all...] |
| amdgpu_cik_ih.c | 47 * host is currently reading, and a wptr (write pointer)
51 * wptr. When there is an interrupt, the host then starts
93 /* set rptr, wptr to 0 */
146 /* set rptr, wptr to 0 */
182 * cik_ih_get_wptr - get the IH ring buffer wptr
186 * Get the IH ring buffer wptr from either the register
190 * Returns the value of the wptr.
195 u32 wptr, tmp; local in function:cik_ih_get_wptr
197 wptr = le32_to_cpu(*ih->wptr_cpu);
199 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK)
[all...] |
| amdgpu_cz_ih.c | 47 * host is currently reading, and a wptr (write pointer)
51 * wptr. When there is an interrupt, the host then starts
93 /* set rptr, wptr to 0 */
148 /* set rptr, wptr to 0 */
184 * cz_ih_get_wptr - get the IH ring buffer wptr
188 * Get the IH ring buffer wptr from either the register
192 * Returns the value of the wptr.
197 u32 wptr, tmp; local in function:cz_ih_get_wptr
199 wptr = le32_to_cpu(*ih->wptr_cpu);
201 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
[all...] |
| amdgpu_iceland_ih.c | 47 * host is currently reading, and a wptr (write pointer)
51 * wptr. When there is an interrupt, the host then starts
93 /* set rptr, wptr to 0 */
148 /* set rptr, wptr to 0 */
184 * iceland_ih_get_wptr - get the IH ring buffer wptr
188 * Get the IH ring buffer wptr from either the register
192 * Returns the value of the wptr.
197 u32 wptr, tmp; local in function:iceland_ih_get_wptr
199 wptr = le32_to_cpu(*ih->wptr_cpu);
201 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
[all...] |
| amdgpu_si_ih.c | 113 u32 wptr, tmp; local in function:si_ih_get_wptr
115 wptr = le32_to_cpu(*ih->wptr_cpu);
117 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
118 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
120 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
121 ih->rptr = (wptr + 16) & ih->ptr_mask;
126 return (wptr & ih->ptr_mask);
|
| amdgpu_tonga_ih.c | 47 * host is currently reading, and a wptr (write pointer)
51 * wptr. When there is an interrupt, the host then starts
89 /* set rptr, wptr to 0 */
146 /* set rptr, wptr to 0 */
186 * tonga_ih_get_wptr - get the IH ring buffer wptr
190 * Get the IH ring buffer wptr from either the register
194 * Returns the value of the wptr.
199 u32 wptr, tmp; local in function:tonga_ih_get_wptr
201 wptr = le32_to_cpu(*ih->wptr_cpu);
203 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
[all...] |
| amdgpu_navi10_ih.c | 74 /* set rptr, wptr to 0 */
152 /* set rptr, wptr to 0 */
205 * navi10_ih_get_wptr - get the IH ring buffer wptr
209 * Get the IH ring buffer wptr from either the register
212 * Returns the value of the wptr.
217 u32 wptr, reg, tmp; local in function:navi10_ih_get_wptr
219 wptr = le32_to_cpu(*ih->wptr_cpu);
221 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
225 wptr = RREG32_NO_KIQ(reg);
226 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)
[all...] |
| amdgpu_vega10_ih.c | 123 /* set rptr, wptr to 0 */
142 /* set rptr, wptr to 0 */
163 /* set rptr, wptr to 0 */
274 /* set rptr, wptr to 0 */
303 /* set rptr, wptr to 0 */
330 /* set rptr, wptr to 0 */
371 * vega10_ih_get_wptr - get the IH ring buffer wptr
375 * Get the IH ring buffer wptr from either the register
378 * Returns the value of the wptr.
383 u32 wptr, reg, tmp local in function:vega10_ih_get_wptr
548 uint32_t wptr = cpu_to_le32(entry->src_data[0]); local in function:vega10_ih_self_irq
[all...] |
| amdgpu_sdma_v2_4.c | 211 * Get the current wptr from the hardware (VI+).
216 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; local in function:sdma_v2_4_ring_get_wptr
218 return wptr;
226 * Write the wptr back to the hardware (VI+).
232 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
264 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
471 ring->wptr = 0;
472 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
|
| amdgpu_ring.h | 191 u64 wptr; member in struct:amdgpu_ring
297 ring->ring[ring->wptr++ & ring->buf_mask] = v;
298 ring->wptr &= ring->ptr_mask;
311 occupied = ring->wptr & ring->buf_mask;
328 ring->wptr += count_dw;
329 ring->wptr &= ring->ptr_mask;
|
| amdgpu_sdma_v3_0.c | 367 * Get the current wptr from the hardware (VI+).
372 u32 wptr; local in function:sdma_v3_0_ring_get_wptr
376 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
378 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
381 return wptr;
389 * Write the wptr back to the hardware (VI+).
398 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
399 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
403 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
405 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2)
[all...] |
| amdgpu_sdma_v4_0.c | 664 * Get the current wptr from the hardware (VEGA10+).
669 u64 wptr; local in function:sdma_v4_0_ring_get_wptr
673 wptr = READ_ONCE(*((volatile u64 *)&adev->wb.wb[ring->wptr_offs]));
674 DRM_DEBUG("wptr/doorbell before shift == 0x%016"PRIx64"\n", wptr);
676 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
677 wptr = wptr << 32;
678 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
679 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016"PRIx64"\n"
738 u64 wptr; local in function:sdma_v4_0_page_ring_get_wptr
770 uint64_t wptr = ring->wptr << 2; local in function:sdma_v4_0_page_ring_set_wptr
[all...] |
| amdgpu_sdma_v5_0.c | 247 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
261 cur = (ring->wptr - 1) & ring->buf_mask;
291 * Get the current wptr from the hardware (NAVI10+).
296 volatile u64 *wptr = NULL; local in function:sdma_v5_0_ring_get_wptr
301 wptr = ((volatile u64 *)&adev->wb.wb[ring->wptr_offs]);
302 DRM_DEBUG("wptr/doorbell before shift == 0x%016"PRIx64"\n", *wptr);
303 *wptr = (*wptr) >> 2;
304 DRM_DEBUG("wptr/doorbell after shift == 0x%016"PRIx64"\n", *wptr)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_kernel_queue.c | 237 uint32_t wptr, rptr; local in function:kq_acquire_packet_buffer
241 /* When rptr == wptr, the buffer is empty.
242 * When rptr == wptr + 1, the buffer is full.
243 * It is always rptr that advances to the position of wptr, rather than
247 wptr = kq->pending_wptr;
253 pr_debug("wptr: %d\n", wptr);
256 available_size = (rptr + queue_size_dwords - 1 - wptr) %
267 if (wptr + packet_size_in_dwords >= queue_size_dwords) {
275 while (wptr > 0)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/inc/ |
| dmub_rb.h | 126 uint32_t wptr = rb->wrpt; local in function:dmub_rb_flush_pending
128 while (rptr != wptr) {
|
| /src/sys/dev/podulebus/ |
| if_ei.c | 253 u_int16_t *wptr; local in function:ei_copyin
259 wptr = dest;
270 ei_atopo(src) / 2, wptr, cnt / 2);
273 wptr += cnt / 2;
280 *(u_int8_t *)wptr =
292 const u_int16_t *wptr; local in function:ei_copyout
307 wptr = src;
318 ei_atopo(dest) / 2, wptr, cnt / 2);
320 wptr += cnt / 2;
|
| sec.c | 238 uint16_t tmp, *wptr; local in function:sec_copyin
257 wptr = dest;
267 SEC_SRAM + src % SEC_PAGESIZE / 2, wptr, cnt / 2);
269 wptr += cnt / 2;
274 *(u_int8_t *)wptr =
284 const uint16_t *wptr; local in function:sec_copyout
306 wptr = src;
316 dest % SEC_PAGESIZE / 2, wptr, cnt / 2);
317 wptr += cnt / 2;
330 tmp |= *(uint8_t const *)wptr;
[all...] |
| /src/lib/libedit/ |
| tokenizer.c | 89 Char *wptr, *wmax; /* Space and limit on the word buffer */ local in function:TYPE
107 *tok->wptr = '\0';
108 if ((tok->flags & TOK_KEEP) || tok->wptr != tok->wstart) {
111 tok->wstart = ++tok->wptr;
150 tok->wptr = tok->wspace;
167 tok->wptr = tok->wspace;
219 co = (int)(tok->wptr - tok->wstart);
237 *tok->wptr++ = *ptr;
241 *tok->wptr++ = *ptr;
246 *tok->wptr++ = *ptr
[all...] |
| /src/sys/arch/arm/gemini/ |
| gemini_gmac.c | 622 uint16_t wptr; local in function:gmac_hwqueue_produce
629 aprint_debug("gmac_hwqueue_produce(%p, %zu): rptr=%u(%u) wptr old=%u",
634 for (wptr = hwq->hwq_wptr;
636 count--, wptr = (wptr + 1) & (hwq->hwq_size - 1)) {
637 KASSERT(((wptr + 1) & (hwq->hwq_size - 1)) != hwq->hwq_rptr);
639 sizeof(gmac_desc_t [hwq->hwq_qoff + wptr]),
644 hwq->hwq_wptr = wptr;
724 "map %p(%zu): can't map rx mbuf(%p) wptr=%u: %d\n",
926 * Update hardware's copy of rptr. (wptr is RO)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_ring.c | 47 * GPU is currently reading, and a wptr (write pointer)
51 * wptr. The GPU then starts fetching commands and executes
93 ring->ring_free_dw -= ring->wptr;
134 ring->wptr_old = ring->wptr;
170 * Update the wptr (write pointer) to tell the GPU to
182 while (ring->wptr & ring->align_mask) {
212 * radeon_ring_undo - reset the wptr
216 * Reset the driver's copy of the wptr (all asics).
220 ring->wptr = ring->wptr_old;
224 * radeon_ring_unlock_undo - reset the wptr and unlock the rin
477 uint32_t rptr, wptr, rptr_next; local in function:radeon_debugfs_ring_info
[all...] |
| radeon_ni.c | 1444 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1503 u32 wptr; local in function:cayman_gfx_get_wptr
1506 wptr = RREG32(CP_RB0_WPTR);
1508 wptr = RREG32(CP_RB1_WPTR);
1510 wptr = RREG32(CP_RB2_WPTR);
1512 return wptr;
1519 WREG32(CP_RB0_WPTR, ring->wptr);
1522 WREG32(CP_RB1_WPTR, ring->wptr);
1525 WREG32(CP_RB2_WPTR, ring->wptr);
1725 ring->wptr = 0
[all...] |
| /src/sys/dev/isa/ |
| if_ix.c | 242 uint16_t *wptr = dst; local in function:ix_copyin
259 wptr = (uint16_t*)bptr;
263 *wptr = bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT);
264 wptr++;
286 const uint16_t *wptr = src; local in function:ix_copyout
303 wptr = (const uint16_t*)bptr;
307 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, *wptr);
308 wptr++;
|
| /src/sys/net/ |
| ppp-deflate.c | 234 u_char *rptr, *wptr; local in function:z_compress
262 wptr = mtod(m, u_char *);
267 wptr[0] = PPP_ADDRESS(rptr);
268 wptr[1] = PPP_CONTROL(rptr);
269 wptr[2] = PPP_COMP >> 8;
270 wptr[3] = PPP_COMP;
271 wptr += PPP_HDRLEN;
272 wptr[0] = state->seqno >> 8;
273 wptr[1] = state->seqno;
274 wptr += 2
466 u_char *rptr, *wptr; local in function:z_decompress
[all...] |
| bsd-comp.c | 467 u_char *rptr, *wptr; local in function:bsd_compress
474 if (wptr) { \
475 *wptr++ = (v); \
476 if (wptr >= cp_end) { \
477 m->m_len = wptr - mtod(m, u_char *); \
484 wptr = mtod(m, u_char *); \
485 cp_end = wptr + M_TRAILINGSPACE(m); \
487 wptr = NULL; \
527 wptr = mtod(m, u_char *);
528 cp_end = wptr + M_TRAILINGSPACE(m)
805 u_char *p, *rptr, *wptr; local in function:bsd_decompress
[all...] |
| /src/sys/external/bsd/ipf/netinet/ |
| ip_ftp_pxy.c | 597 char *rptr, *wptr, cmd[6], c; local in function:ipf_p_ftp_client
604 wptr = f->ftps_wptr;
665 while ((*rptr++ != '\n') && (rptr < wptr))
956 char *rptr, *wptr; local in function:ipf_p_ftp_server
963 wptr = f->ftps_wptr;
1020 while ((*rptr++ != '\n') && (rptr < wptr))
1230 char *rptr, *wptr, *s; local in function:ipf_p_ftp_process
1420 wptr = f->ftps_wptr;
1426 len = MIN(mlen, sizeof(f->ftps_buf) - (wptr - rptr));
1429 COPYDATA(m, off, len, wptr);
[all...] |
