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    Searched refs:ARRAY_1D_TILED_THIN1 (Results 1 - 25 of 39) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v8_0.c 2137 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2147 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2159 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2207 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2309 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2323 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2339 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2395 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2498 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2512 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
    [all...]
amdgpu_gfx_v6_0.c 457 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
485 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
512 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
681 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
721 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
753 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
887 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
915 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
942 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1111 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
    [all...]
amdgpu_gfx_v7_0.c 1083 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1093 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1105 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1153 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1250 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1264 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1279 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1333 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1436 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1446 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
    [all...]
amdgpu_dce_v10_0.c 2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2015 ARRAY_1D_TILED_THIN1);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_cik.c 2403 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2416 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2431 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2446 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2546 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2559 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2574 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2589 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2690 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2703 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
    [all...]
radeon_evergreen_cs.c 107 return ARRAY_1D_TILED_THIN1;
318 case ARRAY_1D_TILED_THIN1:
339 case ARRAY_1D_TILED_THIN1:
914 surf.mode = ARRAY_1D_TILED_THIN1;
921 case ARRAY_1D_TILED_THIN1:
radeon_si.c 2563 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2608 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2644 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2778 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2823 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2859 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
cikd.h 1223 # define ARRAY_1D_TILED_THIN1 2
sid.h 1185 # define ARRAY_1D_TILED_THIN1 2
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
bif_5_1_enum.h 528 ARRAY_1D_TILED_THIN1 = 0x2,
bif_5_0_enum.h 38 ARRAY_1D_TILED_THIN1 = 0x2,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
gmc_8_2_enum.h 528 ARRAY_1D_TILED_THIN1 = 0x2,
gmc_8_1_enum.h 38 ARRAY_1D_TILED_THIN1 = 0x2,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_8_0_enum.h 528 ARRAY_1D_TILED_THIN1 = 0x2,
smu_7_1_0_enum.h 81 ARRAY_1D_TILED_THIN1 = 0x2,
smu_7_1_1_enum.h 88 ARRAY_1D_TILED_THIN1 = 0x2,
smu_7_1_2_enum.h 88 ARRAY_1D_TILED_THIN1 = 0x2,
smu_7_1_3_enum.h 85 ARRAY_1D_TILED_THIN1 = 0x2,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_6_0_enum.h 541 ARRAY_1D_TILED_THIN1 = 0x2,
uvd_5_0_enum.h 51 ARRAY_1D_TILED_THIN1 = 0x2,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_8_0_enum.h 38 ARRAY_1D_TILED_THIN1 = 0x2,
dce_10_0_enum.h 613 ARRAY_1D_TILED_THIN1 = 0x2,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_enum.h 223 ARRAY_1D_TILED_THIN1 = 0x2,
oss_3_0_1_enum.h 924 ARRAY_1D_TILED_THIN1 = 0x2,
oss_3_0_enum.h 337 ARRAY_1D_TILED_THIN1 = 0x2,

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