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    Searched refs:ARRAY_2D_TILED_THIN1 (Results 1 - 25 of 39) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v6_0.c 425 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
433 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
441 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
449 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
460 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
468 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
476 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
488 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
496 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
504 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
    [all...]
amdgpu_gfx_v8_0.c 2117 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2121 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2125 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2129 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2133 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2151 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2163 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2211 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2289 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2293 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
    [all...]
amdgpu_gfx_v7_0.c 1063 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1067 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1075 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1079 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1096 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1108 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1156 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1230 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1234 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
    [all...]
amdgpu_dce_v10_0.c 1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2004 ARRAY_2D_TILED_THIN1);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_si.c 2527 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2536 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2545 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2554 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2572 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2581 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2590 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2617 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2626 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2635 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
    [all...]
radeon_cik.c 2383 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2387 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2391 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2395 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2399 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2419 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2434 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2449 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2526 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2530 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
    [all...]
radeon_evergreen_cs.c 105 return ARRAY_2D_TILED_THIN1;
320 case ARRAY_2D_TILED_THIN1:
335 case ARRAY_2D_TILED_THIN1:
912 case ARRAY_2D_TILED_THIN1:
cikd.h 1224 # define ARRAY_2D_TILED_THIN1 4
sid.h 1186 # define ARRAY_2D_TILED_THIN1 4
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
bif_5_1_enum.h 530 ARRAY_2D_TILED_THIN1 = 0x4,
bif_5_0_enum.h 40 ARRAY_2D_TILED_THIN1 = 0x4,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
gmc_8_2_enum.h 530 ARRAY_2D_TILED_THIN1 = 0x4,
gmc_8_1_enum.h 40 ARRAY_2D_TILED_THIN1 = 0x4,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_8_0_enum.h 530 ARRAY_2D_TILED_THIN1 = 0x4,
smu_7_1_0_enum.h 83 ARRAY_2D_TILED_THIN1 = 0x4,
smu_7_1_1_enum.h 90 ARRAY_2D_TILED_THIN1 = 0x4,
smu_7_1_2_enum.h 90 ARRAY_2D_TILED_THIN1 = 0x4,
smu_7_1_3_enum.h 87 ARRAY_2D_TILED_THIN1 = 0x4,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_6_0_enum.h 543 ARRAY_2D_TILED_THIN1 = 0x4,
uvd_5_0_enum.h 53 ARRAY_2D_TILED_THIN1 = 0x4,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_8_0_enum.h 40 ARRAY_2D_TILED_THIN1 = 0x4,
dce_10_0_enum.h 615 ARRAY_2D_TILED_THIN1 = 0x4,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_4_enum.h 225 ARRAY_2D_TILED_THIN1 = 0x4,
oss_3_0_1_enum.h 926 ARRAY_2D_TILED_THIN1 = 0x4,
oss_3_0_enum.h 339 ARRAY_2D_TILED_THIN1 = 0x4,

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