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    Searched refs:ARRAY_MODE (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v6_0.c 84 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
425 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
433 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
441 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
449 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
457 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
460 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
468 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
476 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
483 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED)
    [all...]
amdgpu_gfx_v8_0.c 75 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
2117 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2121 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2125 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2129 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2133 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2137 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2141 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2145 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2147 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)
    [all...]
amdgpu_gfx_v7_0.c 1063 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1067 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1075 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1079 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1083 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1086 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1091 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1093 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1096 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)
    [all...]
amdgpu_fb.c 173 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
cikd.h 193 # define ARRAY_MODE(x) ((x) << 2)
amdgpu_dce_v10_0.c 1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
amdgpu_dce_v11_0.c 2035 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2055 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
amdgpu_dce_v6_0.c 1942 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1957 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
amdgpu_dce_v8_0.c 1914 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1930 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
sid.h 1180 # define ARRAY_MODE(x) ((x) << 2)
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_cik.c 2383 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2387 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2391 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2395 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2399 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2403 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2406 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2410 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2414 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2416 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)
    [all...]
radeon_si.c 2527 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2536 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2545 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2554 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2563 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2572 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2581 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2590 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2599 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2608 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)
    [all...]
cikd.h 1220 # define ARRAY_MODE(x) ((x) << 2)
sid.h 1182 # define ARRAY_MODE(x) ((x) << 2)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm.c 3262 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
3273 tiling_info->gfx8.array_mode =
3281 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
3283 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
navi10_enum.h 1672 * ARRAY_MODE enum
1675 typedef enum ARRAY_MODE {
1692 } ARRAY_MODE;

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