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    Searched refs:AR_PHY_AGC_CONTROL (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/isc/atheros_hal/dist/ar5416/
ar5416_cal.c 180 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
187 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
190 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
200 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
207 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
210 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
224 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
522 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
523 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
524 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF)
    [all...]
  /src/sys/external/isc/atheros_hal/dist/ar5211/
ar5211phy.h 40 #define AR_PHY_AGC_CONTROL 0x9860 /* PHY chip calibration and noise floor setting */
ar5211_reset.c 471 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
472 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
473 (void) ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0);
879 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
880 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
899 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0)
909 OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
955 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
1015 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1016 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) |
    [all...]
  /src/sys/dev/ic/
arn9285.c 598 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL,
601 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
603 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) &
616 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
618 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
620 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) &
629 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
arn5416.c 331 AR_SETBITS(sc, AR_PHY_AGC_CONTROL,
335 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
338 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) &
347 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL,
arn9380.c 535 reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
537 AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);
547 reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
549 AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);
arn9003.c 2078 if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
2127 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
2128 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
2129 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2132 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
2153 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
2154 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
2155 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2163 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2192 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL)
    [all...]
arn5008.c 1910 if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
1942 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
1943 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1944 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1947 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
1968 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
1969 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1970 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1979 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
arn5008reg.h 79 #define AR_PHY_AGC_CONTROL 0x9860
333 /* Bits for AR_PHY_AGC_CONTROL. */
arn9003reg.h 151 #define AR_PHY_AGC_CONTROL 0x0a2c4
616 /* Bits for AR_PHY_AGC_CONTROL. */
  /src/sys/external/isc/atheros_hal/dist/ar5212/
ar5212_reset.c 522 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
523 OS_REG_READ(ah, AR_PHY_AGC_CONTROL)
570 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
791 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1270 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
1323 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
1324 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1325 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1327 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0)) {
1330 __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
    [all...]
ar5212phy.h 112 #define AR_PHY_AGC_CONTROL 0x9860 /* chip calibration and noise floor setting */
ar5212_misc.c 1086 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
  /src/sys/external/isc/atheros_hal/dist/ar5312/
ar5312_reset.c 485 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
486 OS_REG_READ(ah, AR_PHY_AGC_CONTROL)
533 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {

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