HomeSort by: relevance | last modified time | path
    Searched refs:AR_SETBITS (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/dev/ic/
arn9285.c 426 AR_SETBITS(sc, AR_PHY(2), 1 << 27);
428 AR_SETBITS(sc, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC);
429 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1);
430 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I);
431 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF);
465 AR_SETBITS(sc, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS(i));
469 AR_SETBITS(sc, AR9285_AN_RF2G6,
478 AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
482 AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
488 AR_SETBITS(sc, AR9285_AN_RF2G6, 1)
    [all...]
athn.c 515 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS);
533 AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA);
749 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
759 AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
775 AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
857 AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
966 AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
1189 AR_SETBITS(sc, sc->sc_gpio_input_en_off,
1200 AR_SETBITS(sc, sc->sc_gpio_input_en_off,
1238 AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE)
    [all...]
arn9287.c 546 AR_SETBITS(sc, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
597 AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
599 AR_SETBITS(sc, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
602 AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
623 AR_SETBITS(sc, AR_MAC_PCU_LOGIC_ANALYZER,
630 AR_SETBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
arn9380.c 284 AR_SETBITS(sc, AR_PHY_65NM_CH0_SYNTH4,
465 AR_SETBITS(sc, AR_RTC_REG_CONTROL1,
469 AR_SETBITS(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_SWREG_PRD);
653 AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER);
669 AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI);
685 AR_SETBITS(sc, AR_PHY_TIMING4,
arn9003.c 586 AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
591 AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB);
593 AR_SETBITS(sc, AR_GPIO_INTR_POL,
1972 AR_SETBITS(sc, AR_PHY_CCK_DETECT,
2000 AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
2129 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2153 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
2154 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
2155 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2163 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF)
    [all...]
arn5008.c 410 AR_SETBITS(sc, AR7010_GPIO_OE, 1 << pin);
456 AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
461 AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB);
463 AR_SETBITS(sc, AR_GPIO_INTR_POL,
1798 AR_SETBITS(sc, AR_PHY_CCK_DETECT,
1828 AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
1944 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1968 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
1969 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1970 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF)
    [all...]
arn5416.c 331 AR_SETBITS(sc, AR_PHY_AGC_CONTROL,
335 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
346 AR_SETBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
698 AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
arn9280.c 495 AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
athnreg.h 1468 #define AR_SETBITS(sc, reg, mask) \

Completed in 23 milliseconds