| /src/sys/arch/arm/nxp/ |
| imx6_clk.c | 926 CLK_DIV("periph_clk2", "periph_clk2_sel", CBCDR, PERIPH_CLK2_PODF),
927 CLK_DIV("periph2_clk2", "periph2_clk2_sel", CBCDR, PERIPH2_CLK2_PODF),
928 CLK_DIV("ipg", "ahb", CBCDR, IPG_PODF),
929 CLK_DIV("esai_pred", "esai_sel", CS1CDR, ESAI_CLK_PRED),
930 CLK_DIV("esai_podf", "esai_pred", CS1CDR, ESAI_CLK_PODF),
931 CLK_DIV("asrc_pred", "asrc_sel", CDCDR, SPDIF1_CLK_PRED),
932 CLK_DIV("asrc_podf", "asrc_pred", CDCDR, SPDIF1_CLK_PODF),
933 CLK_DIV("spdif_pred", "spdif_sel", CDCDR, SPDIF0_CLK_PRED),
934 CLK_DIV("spdif_podf", "spdif_pred", CDCDR, SPDIF0_CLK_PODF),
935 CLK_DIV("ecspi_root", "pll3_60m", CSCDR2, ECSPI_CLK_PODF)
[all...] |
| imx6sx_clk.c | 1015 CLK_DIV("periph_clk2", "periph_clk2_sel", CBCDR, PERIPH_CLK2_PODF),
1016 CLK_DIV("periph2_clk2", "periph2_clk2_sel", CBCDR, PERIPH2_CLK2_PODF),
1018 CLK_DIV("ipg", "ahb", CBCDR, IPG_PODF),
1019 CLK_DIV("gpu_core_podf", "gpu_core_sel", CBCMR, GPU3D_SHADER_PODF),
1020 CLK_DIV("gpu_axi_podf", "gpu_axi_sel", CBCMR, GPU3D_CORE_PODF),
1021 CLK_DIV("lcdif1_podf", "lcdif1_pred", CBCMR, GPU2D_CORE_CLK_PODF),
1022 CLK_DIV("esai_pred", "esai_sel", CS1CDR, ESAI_CLK_PRED),
1023 CLK_DIV("esai_podf", "esai_pred", CS1CDR, ESAI_CLK_PODF),
1024 CLK_DIV("spdif_pred", "spdif_sel", CDCDR, SPDIF0_CLK_PRED),
1025 CLK_DIV("spdif_podf", "spdif_pred", CDCDR, SPDIF0_CLK_PODF)
[all...] |
| imx6_ccmvar.h | 210 #define CLK_DIV(_name, _parent, _reg, _mask) { \
|
| /src/sys/arch/arm/samsung/ |
| exynos5410_clock.c | 179 #define CLK_DIV(_name, _parent, _reg, _bits) \
301 CLK_DIV("div_arm", "mout_cpu", EXYNOS5410_DIV_CPU0, __BITS(2,0)),
302 CLK_DIV("div_arm2", "div_arm", EXYNOS5410_DIV_CPU0, __BITS(30,28)),
304 CLK_DIV("div_acp", "div_arm2", EXYNOS5410_DIV_CPU0, __BITS(10,8)),
305 CLK_DIV("div_cpud", "div_arm2", EXYNOS5410_DIV_CPU0, __BITS(6,4)),
306 CLK_DIV("div_atb", "div_arm2", EXYNOS5410_DIV_CPU0, __BITS(18,16)),
307 CLK_DIV("pclk_dbg", "div_arm2", EXYNOS5410_DIV_CPU0, __BITS(22,20)),
309 CLK_DIV("div_kfc", "mout_kfc", EXYNOS5410_DIV_KFC0, __BITS(2,0)),
310 CLK_DIV("div_aclk", "div_kfc", EXYNOS5410_DIV_KFC0, __BITS(6,4)),
311 CLK_DIV("div_pclk", "div_kfc", EXYNOS5410_DIV_KFC0, __BITS(22,20))
[all...] |
| exynos5422_clock.c | 311 #define CLK_DIV(_name, _parent, _reg, _bits) { \
497 CLK_DIV("dout_aclk66", "mout_aclk66", EXYNOS5422_DIV_TOP1, __BITS(13,8)),
498 CLK_DIV("dout_aclk200_fsys", "mout_aclk200_fsys", EXYNOS5422_DIV_TOP0, __BITS(30,28)),
499 CLK_DIV("dout_aclk200_fsys2", "mout_aclk200_fsys2", EXYNOS5422_DIV_TOP0, __BITS(14,12)),
501 CLK_DIV("dout_usbphy301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(15,12)),
502 CLK_DIV("dout_usbphy300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(19,16)),
503 CLK_DIV("dout_usbd301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(23,20)),
504 CLK_DIV("dout_usbd300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(27,24)),
505 CLK_DIV("dout_mmc0", "mout_mmc0", EXYNOS5422_DIV_FSYS1, __BITS(9,0)),
506 CLK_DIV("dout_mmc1", "mout_mmc1", EXYNOS5422_DIV_FSYS1, __BITS(19,10))
[all...] |
| /src/sys/arch/arm/nvidia/ |
| tegra124_car.c | 332 #define CLK_DIV(_name, _parent, _reg, _bits) { \
534 CLK_DIV("div_uarta", "mux_uarta",
536 CLK_DIV("div_uartb", "mux_uartb",
538 CLK_DIV("div_uartc", "mux_uartc",
540 CLK_DIV("div_uartd", "mux_uartd",
542 CLK_DIV("div_sdmmc1", "mux_sdmmc1",
544 CLK_DIV("div_sdmmc2", "mux_sdmmc2",
546 CLK_DIV("div_sdmmc3", "mux_sdmmc3",
548 CLK_DIV("div_sdmmc4", "mux_sdmmc4",
550 CLK_DIV("div_i2c1", "mux_i2c1",
[all...] |
| tegra210_car.c | 344 #define CLK_DIV(_name, _parent, _reg, _bits) { \
548 CLK_DIV("DIV_UARTA", "MUX_UARTA",
550 CLK_DIV("DIV_UARTB", "MUX_UARTB",
552 CLK_DIV("DIV_UARTC", "MUX_UARTC",
554 CLK_DIV("DIV_UARTD", "MUX_UARTD",
557 CLK_DIV("DIV_SDMMC1", "MUX_SDMMC1",
559 CLK_DIV("DIV_SDMMC2", "MUX_SDMMC2",
561 CLK_DIV("DIV_SDMMC3", "MUX_SDMMC3",
563 CLK_DIV("DIV_SDMMC4", "MUX_SDMMC4",
566 CLK_DIV("DIV_I2C1", "MUX_I2C1"
[all...] |
