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    Searched refs:CLK_S (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
rv740d.h 106 #define CLK_S(x) ((x) << 4)
rv730d.h 136 #define CLK_S(x) ((x) << 4)
radeon_rv730_dpm.c 101 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:rv730_populate_sclk_value
102 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
105 cg_spll_spread_spectrum |= CLK_S(clk_s);
177 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:rv730_populate_mclk_value
178 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000);
181 mpll_ss |= CLK_S(clk_s);
radeon_rv740_dpm.c 169 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:rv740_populate_sclk_value
170 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
173 cg_spll_spread_spectrum |= CLK_S(clk_s);
258 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); local in function:rv740_populate_mclk_value
260 (dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000);
266 mpll_ss2 |= CLKS(clk_s);
nid.h 677 #define CLK_S(x) ((x) << 4)
cikd.h 271 #define CLK_S(x) ((x) << 4)
sid.h 117 #define CLK_S(x) ((x) << 4)
radeon_ni_dpm.c 2050 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:ni_calculate_sclk_params
2051 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2054 cg_spll_spread_spectrum |= CLK_S(clk_s);
2102 u32 clk_s; local in function:ni_init_smc_spll_table
2122 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2132 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2135 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2149 ((clk_s << SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2248 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate) local in function:ni_populate_mclk_value
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radeon_ci_dpm.c 3199 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:ci_calculate_sclk_params
3200 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3203 cg_spll_spread_spectrum |= CLK_S(clk_s);
radeon_si_dpm.c 2858 u32 clk_s, clk_v; local in function:si_init_smc_spll_table
2878 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2889 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2902 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
4832 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:si_calculate_sclk_params
4833 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4836 cg_spll_spread_spectrum |= CLK_S(clk_s);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h 119 #define CLK_S(x) ((x) << 4)
amdgpu_si_dpm.c 2958 u32 clk_s, clk_v; local in function:si_init_smc_spll_table
2977 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2988 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
3001 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
5296 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:si_calculate_sclk_params
5297 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5300 cg_spll_spread_spectrum |= CLK_S(clk_s);

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