Searched refs:CLK_TOP_SYSPLL1_D2 (Results 1 - 10 of 10) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dmt7629-clk.h37 #define CLK_TOP_SYSPLL1_D2 25 macro
H A Dmt6765-clk.h39 #define CLK_TOP_SYSPLL1_D2 2 macro
H A Dmt6797-clk.h49 #define CLK_TOP_SYSPLL1_D2 37 macro
H A Dmt7622-clk.h33 #define CLK_TOP_SYSPLL1_D2 19 macro
H A Dmt8173-clk.h56 #define CLK_TOP_SYSPLL1_D2 44 macro
H A Dmediatek,mt6795-clk.h54 #define CLK_TOP_SYSPLL1_D2 41 macro
H A Dmt2701-clk.h18 #define CLK_TOP_SYSPLL1_D2 6 macro
H A Dmt2712-clk.h39 #define CLK_TOP_SYSPLL1_D2 6 macro
H A Dmediatek,mt8365-clk.h19 #define CLK_TOP_SYSPLL1_D2 7 macro
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi268 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
322 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
391 <&topckgen CLK_TOP_SYSPLL1_D2>,

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