Searched refs:CLK_TOP_UNIVPLL1_D2 (Results 1 - 12 of 12) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dmt8135-clk.h45 #define CLK_TOP_UNIVPLL1_D2 32 macro
H A Dmt7629-clk.h52 #define CLK_TOP_UNIVPLL1_D2 40 macro
H A Dmt6765-clk.h60 #define CLK_TOP_UNIVPLL1_D2 23 macro
H A Dmt6797-clk.h70 #define CLK_TOP_UNIVPLL1_D2 58 macro
H A Dmt7622-clk.h46 #define CLK_TOP_UNIVPLL1_D2 32 macro
H A Dmt8173-clk.h75 #define CLK_TOP_UNIVPLL1_D2 63 macro
H A Dmediatek,mt6795-clk.h73 #define CLK_TOP_UNIVPLL1_D2 60 macro
H A Dmt2701-clk.h38 #define CLK_TOP_UNIVPLL1_D2 26 macro
H A Dmt2712-clk.h59 #define CLK_TOP_UNIVPLL1_D2 26 macro
H A Dmediatek,mt8365-clk.h35 #define CLK_TOP_UNIVPLL1_D2 23 macro
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
324 <&topckgen CLK_TOP_UNIVPLL1_D2>;
392 <&topckgen CLK_TOP_UNIVPLL1_D2>;
468 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi322 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;

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