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    Searched refs:CLK_TOP_UNIVPLL1_D2 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
mt8135-clk.h 45 #define CLK_TOP_UNIVPLL1_D2 32
mt7629-clk.h 52 #define CLK_TOP_UNIVPLL1_D2 40
mt6765-clk.h 60 #define CLK_TOP_UNIVPLL1_D2 23
mt6797-clk.h 70 #define CLK_TOP_UNIVPLL1_D2 58
mt7622-clk.h 46 #define CLK_TOP_UNIVPLL1_D2 32
mt8173-clk.h 75 #define CLK_TOP_UNIVPLL1_D2 63
mt2701-clk.h 38 #define CLK_TOP_UNIVPLL1_D2 26
mt2712-clk.h 59 #define CLK_TOP_UNIVPLL1_D2 26
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
mt7629.dtsi 101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
325 <&topckgen CLK_TOP_UNIVPLL1_D2>;
388 <&topckgen CLK_TOP_UNIVPLL1_D2>;
472 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
mt2712e.dtsi 322 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;

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