| /src/sys/dev/pci/ |
| if_vte.c | 347 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0)
356 *val = CSR_READ_2(sc, VTE_MMRD);
371 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0)
444 mid = CSR_READ_2(sc, VTE_MID0L);
447 mid = CSR_READ_2(sc, VTE_MID0M);
450 mid = CSR_READ_2(sc, VTE_MID0H);
873 mcr = CSR_READ_2(sc, VTE_MCR0);
898 CSR_READ_2(sc, VTE_CNT_RX_DONE);
899 CSR_READ_2(sc, VTE_CNT_MECNT0);
900 CSR_READ_2(sc, VTE_CNT_MECNT1)
[all...] |
| if_kse.c | 69 #define CSR_READ_2(sc, off) \
436 i = CSR_READ_2(sc, MARL);
439 i = CSR_READ_2(sc, MARM);
442 i = CSR_READ_2(sc, MARH);
801 i = CSR_READ_2(sc, SGCR3);
1331 uint16_t p1sr = CSR_READ_2(sc, P1SR);
1382 printf("p1sr: %04x, p2sr: %04x\n", CSR_READ_2(sc, P1SR), CSR_READ_2(sc, P2SR));
1425 *val = CSR_READ_2(sc, phy1csr[reg]);
1448 uint16_t p1sr = CSR_READ_2(sc, P1SR)
[all...] |
| if_stge.c | 232 #define CSR_READ_2(_sc, reg) \
583 enaddr[0] = CSR_READ_2(sc, STGE_StationAddress0) & 0xff;
584 enaddr[1] = CSR_READ_2(sc, STGE_StationAddress0) >> 8;
585 enaddr[2] = CSR_READ_2(sc, STGE_StationAddress1) & 0xff;
586 enaddr[3] = CSR_READ_2(sc, STGE_StationAddress1) >> 8;
587 enaddr[4] = CSR_READ_2(sc, STGE_StationAddress2) & 0xff;
588 enaddr[5] = CSR_READ_2(sc, STGE_StationAddress2) >> 8;
1089 if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0)
1093 isr = CSR_READ_2(sc, STGE_IntStatusAck);
1437 (u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors))
[all...] |
| if_vtevar.h | 157 #define CSR_READ_2(_sc, reg) \
|
| if_vr.c | 295 #define CSR_READ_2(sc, reg) \
338 CSR_READ_2(sc, reg) | (x))
342 CSR_READ_2(sc, reg) & ~(x))
425 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON | VR_CMD_RX_ON))
440 if (!(CSR_READ_2(sc, VR_COMMAND) &
529 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
813 if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0)
859 if ((CSR_READ_2(sc, VR_COMMAND) &
929 status = CSR_READ_2(sc, VR_ISR);
|
| if_ipwreg.h | 316 #define CSR_READ_2(sc, reg) \
|
| if_wi_pci.c | 170 if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY))
|
| /src/sys/arch/sandpoint/stand/altboot/ |
| kse.c | 49 #define CSR_READ_2(l, r) in16rb((l)->csr+(r))
138 i = CSR_READ_2(l, MARL);
141 i = CSR_READ_2(l, MARM);
144 i = CSR_READ_2(l, MARH);
157 val = CSR_READ_2(l, P1SR);
267 val = CSR_READ_2(l, P1SR);
|
| stg.c | 44 #define CSR_READ_2(l, r) in16rb((l)->csr+(r))
197 addr[i] = le16toh(CSR_READ_2(l, STGE_EepromData));
245 CSR_READ_2(l, STGE_DebugCtrl) | 0x0200);
247 CSR_READ_2(l, STGE_DebugCtrl) | 0x0010);
249 CSR_READ_2(l, STGE_DebugCtrl) | 0x0020);
552 if ((CSR_READ_2(l, STGE_EepromCtrl) & EC_EepromBusy) == 0)
|
| skg.c | 49 #define CSR_READ_2(l, r) in16rb((l)->csr+(r))
321 reg = CSR_READ_2(l, YUKON_GPCR);
408 v = CSR_READ_2(l, YUKON_SMICR);
414 return CSR_READ_2(l, YUKON_SMIDR);
428 v = CSR_READ_2(l, YUKON_SMICR);
|
| fxp.c | 92 #define CSR_READ_2(l, r) in16rb((l)->iobase+(r))
449 if ((CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &
487 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) &
|
| nvt.c | 50 #define CSR_READ_2(l, r) in16rb((l)->csr+(r))
355 v = CSR_READ_2(l, VR_MIIDATA);
|
| pcn.c | 49 #define CSR_READ_2(l, r) in16rb((l)->csr+(r))
156 (void)CSR_READ_2(l, PCN_16RESET);
|
| vge.c | 50 #define CSR_READ_2(l, r) in16rb((l)->csr+(r))
437 v = CSR_READ_2(l, VR_MIIDATA);
|
| /src/sys/arch/evbarm/stand/boot2440/ |
| dm9000.c | 141 CSR_READ_2(struct local *l, int reg)
348 (void) CSR_READ_2(l, MRCMDX); /* dummy read */
349 mark = CSR_READ_2(l, MRCMDX); /* mark in [7:0] */
357 stat = CSR_READ_2(l, MRCMD); /* stat in [15:8] */
358 len = CSR_READ_2(l, MRCMD);
363 (void) CSR_READ_2(l, MRCMD);
373 val = CSR_READ_2(l, MRCMD);
380 (void) CSR_READ_2(l, MRCMD);
|
| /src/sys/dev/ic/ |
| an.c | 494 if (CSR_READ_2(sc, AN_SW0) != AN_MAGIC) {
496 CSR_READ_2(sc, AN_SW0)));
500 status = CSR_READ_2(sc, AN_EVENT_STAT);
1384 fid = CSR_READ_2(sc, AN_RX_FID);
1544 fid = CSR_READ_2(sc, AN_TX_CMP_FID);
1583 status = CSR_READ_2(sc, AN_LINKSTAT);
1606 if (CSR_READ_2(sc, AN_COMMAND) & AN_CMD_BUSY) {
1609 CSR_READ_2(sc, AN_COMMAND));
1624 if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_CMD)
1629 status = CSR_READ_2(sc, AN_STATUS)
[all...] |
| anvar.h | 53 #define CSR_READ_2(sc, reg) \
|
| wivar.h | 243 #define CSR_READ_2(sc, reg) \
265 #define CSR_READ_2(sc, reg) \
|
| rtl81x9.c | 324 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN;
347 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN)
450 *val = CSR_READ_2(sc, rtk8139_reg);
923 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN;
926 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN;
1183 status = CSR_READ_2(sc, RTK_ISR);
|
| rtl81x9var.h | 287 #define CSR_READ_2(sc, reg) \
|
| bwivar.h | 82 #define CSR_READ_2(sc, reg) \
97 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
102 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
107 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
|
| wi.c | 655 status = CSR_READ_2(sc, WI_EVENT_STAT);
691 status = CSR_READ_2(sc, WI_EVENT_STAT);
1661 fid = CSR_READ_2(sc, WI_RX_FID);
1788 fid = CSR_READ_2(sc, WI_TX_CMP_FID);
1864 fid = CSR_READ_2(sc, WI_ALLOC_FID);
1969 fid = CSR_READ_2(sc, WI_TX_CMP_FID);
2024 fid = CSR_READ_2(sc, WI_INFO_FID);
2783 if ((CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY) == 0)
2873 if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_CMD)
2895 status = CSR_READ_2(sc, WI_STATUS)
[all...] |
| i82557var.h | 354 #define CSR_READ_2(sc, reg) \
|
| /src/sys/dev/pcmcia/ |
| if_wi_pcmcia.c | 363 CSR_READ_2(sc, WI_COR) == WI_COR_IOMODE)
446 if (CSR_READ_2(sc, WI_CNTL) == WI_CNTL_AUX_ENA_STAT)
461 if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_CMD)
547 hcr = CSR_READ_2(sc, WI_HCR);
|
| /src/sys/arch/evbarm/ixm1200/ |
| nappi_nppb.c | 60 #define CSR_READ_2(sc, reg) \
|
