Searched refs:DISP_CC_MDSS_CORE_BCR (Results 1 - 19 of 19) sorted by relevance
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
| H A D | qcom,sm6375-dispcc.h | 38 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,dispcc-qcm2290.h | 38 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,sm4450-dispcc.h | 49 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,dispcc-sm8250.h | 72 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,dispcc-sm8350.h | 72 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,dispcc-sm8150.h | 72 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,sm8450-dispcc.h | 97 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,sm8550-dispcc.h | 95 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,sm8650-dispcc.h | 95 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,x1e80100-dispcc.h | 92 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| H A D | qcom,dispcc-sc8280xp.h | 95 #define DISP_CC_MDSS_CORE_BCR 0 macro
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| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/ |
| H A D | qcm2290.dtsi | 1598 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | sc8280xp.dtsi | 4107 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
5394 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
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| H A D | sc8180x.dtsi | 2946 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | sm8350.dtsi | 2750 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | sm8450.dtsi | 3063 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | sm8550.dtsi | 3003 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | sm8650.dtsi | 3614 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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| H A D | x1e80100.dtsi | 4584 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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