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    Searched refs:DMU_BASE (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_navi12_reg_init.c 48 adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DMU_BASE.instance[i]));
amdgpu_navi14_reg_init.c 48 adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DMU_BASE.instance[i]));
  /src/sys/arch/arm/broadcom/
bcm53xx_ccb.c 114 { "bcmdmu", DMU_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT },
bcm53xx_board.c 390 DMU_BASE + DMU_LCPLL_CONTROL1);
392 DMU_BASE + DMU_LCPLL_CONTROL2);
bcm53xx_reg.h 108 #define DMU_BASE 0x00c000
124 #define DMU_BASE 0x03f000
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
navi12_ip_offset.h 69 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
navi14_ip_offset.h 69 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
renoir_ip_offset.h 83 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },

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