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    Searched refs:MHz (Results 1 - 25 of 113) sorted by relevancy

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  /src/sys/dev/ic/
decmonitors.c 38 #define MHz * 1000000
65 175 MHz },
70 75 MHz },
75 74 MHz },
80 69 MHz },
85 65 MHz },
90 50 MHz },
95 40 MHz },
110 135 MHz },
115 110 MHz },
    [all...]
  /src/sys/arch/arm/marvell/
kirkwood.c 238 #define MHz * 1000 * 1000
243 mvTclk = 200 MHz;
244 else /* 166MHz */
251 case 0x00000014: mvPclk = 600 MHz; break;
252 case 0x00000018: mvPclk = 800 MHz; break;
256 mvSysclk = 200 MHz;
259 case 0x00000002: mvPclk = 400 MHz; break;
260 case 0x00000008: mvPclk = 600 MHz; break;
261 case 0x00400008: mvPclk = 800 MHz; break;
262 case 0x0040000a: mvPclk = 1000 MHz; break
    [all...]
mv78xx0.c 215 #define MHz * 1000 * 1000
221 case 0x080: mvTclk = 200 MHz; break;
222 default: mvTclk = 200 MHz; break;
229 case 0x020: mvSysclk = 200 MHz; break;
232 case 0x080: mvSysclk = 400 MHz; break;
233 case 0x0a0: mvSysclk = 250 MHz; break;
234 case 0x0c0: mvSysclk = 300 MHz; break;
241 #undef MHz
dove.c 280 #define MHz * 1000 * 1000
286 case 0x00000000: mvTclk = 166 MHz; break;
287 case 0x00800000: mvTclk = 125 MHz; break;
293 case 0x000000a0: mvPclk = 1000 MHz; break;
294 case 0x000000c0: mvPclk = 933 MHz; break;
295 case 0x000000e0: mvPclk = 933 MHz; break;
296 case 0x00000100: mvPclk = 800 MHz; break;
297 case 0x00000120: mvPclk = 800 MHz; break;
298 case 0x00000140: mvPclk = 800 MHz; break;
299 case 0x00000160: mvPclk = 1067 MHz; break
    [all...]
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/exynos/
exynos5433-tmu.dtsi 56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
80 /* Set maximum frequency as 1400MHz */
86 /* Set maximum frequencyas 1200MHz */
92 /* Set maximum frequency as 1000MHz */
230 /* Set maximum frequency as 1200MHz */
236 /* Set maximum frequency as 1100MHz */
242 /* Set maximum frequency as 1000MHz */
    [all...]
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
integratorcp.dts 49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
121 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
130 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
146 /* TIMER0 runs directly on the 25MHz chrystal *
    [all...]
rk3288-veyron-mickey.dts 86 * and don't let the GPU go faster than 400 MHz.
106 * - 800 MHz (hot)
107 * - 800 MHz - 696 MHz (hotter)
108 * - 696 MHz - min (very hot)
111 * - 800 MHz appears to be a "sweet spot" for me. I can run
113 * - After 696 MHz we stop lowering voltage, so throttling
139 /* At very hot, don't let GPU go over 300 MHz */
180 /* After 1st level throttle the GPU down to as low as 400 MHz */
200 /* When hot, GPU goes down to 300 MHz */
    [all...]
dove-cubox.dts 52 /* 25MHz reference crystal */
97 /* connect xtal input to 25MHz reference */
exynos4412-tiny4412.dts 91 /* Corresponds to 800MHz at freq_table */
96 /* Corresponds to 200MHz at freq_table */
integratorap.dts 31 * that the maximum frequency for this clock is 200 MHz
33 * is actually just hanging the system above 71 MHz.
59 /* 24 MHz chrystal on the Integrator/AP development board */
74 /* The UART clock is 14.74 MHz divided by an ICS525 */
83 /* 24 MHz chrystal on the core module */
99 /* Auxilary oscillator on the core module, 32.369MHz at boot */
125 /* One-bit control for the PCI bus clock (33 or 25 MHz) */
exynos5422-odroidhc1.dts 55 * be: 1600 MHz and 1100 MHz.
70 * further, down to 600 MHz (12 steps for big,
intel-ixp42x-ixdp425.dts 8 * This machine is based on a 533 MHz IXP425.
nuvoton-wpcm450.dtsi 22 clk24m: clock-24mhz {
23 /* 24 MHz dummy clock */
exynos4412-smdk4412.dts 53 /* Corresponds to 800MHz at freq_table */
58 /* Corresponds to 200MHz at freq_table */
exynos5422-odroid-core.dtsi 41 /* derived from 532MHz MPLL */
67 /* derived from 666MHz CPLL */
85 /* derived from 666MHz CPLL */
97 /* derived from 600MHz DPLL */
112 /* derived from 666MHz CPLL */
133 /* derived from 532MHz MPLL */
151 /* derived from 666MHz CPLL */
160 /* derived from 666MHz CPLL */
181 /* derived from 532MHz MPLL */
199 /* derived from 600MHz DPLL *
    [all...]
am5729-beagleboneai.dts 424 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
557 /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
558 /* HS: High speed up to 50 MHz (3.3 V signaling). */
559 /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
560 /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
561 /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
562 /* SDR104: SDR up to 208 MHz (1.8 V signaling) */
563 /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
exynos4210-smdkv310.dts 56 /* Corresponds to 800MHz */
60 /* Corresponds to 200MHz */
nspire.dtsi 102 * display is 1MHz and the CLCDCLK is 48 MHz.
ste-href-tvk1281618-r3.dtsi 133 * Actually the max frequency is 6 MHz, but over 2 MHz the
dm814x-clocks.dtsi 209 /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
275 /* L4_HS 220 MHz*/
293 /* L4_LS 110 MHz */
exynos5260-xyref5260.dts 69 supports-hs200-mode; /* 200 MHz */
  /src/sys/arch/ia64/ia64/
cpu.c 45 #define MHz 1000000L
46 #define GHz (1000L * MHz)
186 aprint_normal("%ld.%02ld-MHz ",
187 (processor_frequency + 4999) / MHz,
188 ((processor_frequency + 4999) / (MHz/100)) % 100);
  /src/sys/arch/mvme68k/stand/sboot/
oc_cksum.s 79 | Sun 3/50 (15MHz) 190 us/KB
80 | Sun 3/180 (16.6MHz) 175 us/KB
81 | Sun 3/60 (20MHz) 134 us/KB
82 | Sun 3/280 (25MHz) 95 us/KB
  /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/cavium-octeon/
octeon_3xxx.dts 362 /* 12MHz, 24MHz and 48MHz allowed */
382 /* 12MHz, 24MHz and 48MHz allowed */
  /src/sys/arch/m68k/m68k/
oc_cksum.s 75 | Sun 3/50 (15MHz) 190 us/KB
76 | Sun 3/180 (16.6MHz) 175 us/KB
77 | Sun 3/60 (20MHz) 134 us/KB
78 | Sun 3/280 (25MHz) 95 us/KB

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