| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| handlers.c | 1982 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1987 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1992 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1997 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
2002 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
2007 MMIO_D(CURCNTR(PIPE_A), D_ALL);
2011 MMIO_D(CURPOS(PIPE_A), D_ALL);
2015 MMIO_D(CURBASE(PIPE_A), D_ALL);
2019 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL);
2032 MMIO_D(DSPCNTR(PIPE_A), D_ALL)
[all...] |
| reg.h | 74 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
84 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
|
| display.c | 51 pipe = PIPE_A;
79 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
310 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
400 [PIPE_A] = PIPE_A_VBLANK,
406 if (pipe < PIPE_A || pipe > PIPE_C)
|
| interrupt.c | 454 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));
|
| cmd_parser.c | 1223 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1225 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1278 info->pipe = PIPE_A;
1291 info->pipe = PIPE_A;
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_pci.c | 103 [PIPE_A] = CURSOR_A_OFFSET, \
108 [PIPE_A] = CURSOR_A_OFFSET, \
114 [PIPE_A] = CURSOR_A_OFFSET, \
121 [PIPE_A] = CURSOR_A_OFFSET, \
128 [PIPE_A] = CURSOR_A_OFFSET, \
166 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
185 .pipe_mask = BIT(PIPE_A), \
224 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
309 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
360 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
[all...] |
| intel_pm.c | 484 case PIPE_A:
971 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
977 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
978 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1021 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
1023 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
1024 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
1025 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1047 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1048 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI)
[all...] |
| intel_device_info.c | 930 runtime->num_scalers[PIPE_A] = 2;
953 runtime->num_sprites[PIPE_A] = 2;
993 enabled_mask &= ~BIT(PIPE_A);
|
| i915_irq.c | 526 i915_enable_pipestat(dev_priv, PIPE_A,
1329 case PIPE_A:
1764 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
2737 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3524 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3698 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3815 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3816 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
| /src/sys/external/bsd/drm/dist/shared-core/ |
| i915_suspend.c | 39 if (pipe == PIPE_A)
48 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
55 if (pipe == PIPE_A)
67 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
74 if (pipe == PIPE_A)
280 i915_save_palette(dev, PIPE_A);
423 i915_restore_palette(dev, PIPE_A);
|
| i915_drv.h | 45 PIPE_A = 0,
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_ddi.c | 1132 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1140 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1141 POSTING_READ(FDI_RX_CTL(PIPE_A));
1146 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1176 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1180 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1181 POSTING_READ(FDI_RX_CTL(PIPE_A));
1187 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1189 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1190 POSTING_READ(FDI_RX_MISC(PIPE_A));
[all...] |
| intel_pipe_crc.c | 184 case PIPE_A:
248 case PIPE_A:
321 pipe_config->hw.active && crtc->pipe == PIPE_A &&
|
| intel_fifo_underrun.c | 138 u32 bit = (pipe == PIPE_A) ?
204 u32 bit = (pch_transcoder == PIPE_A) ?
|
| intel_crt.c | 240 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
268 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
279 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
314 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1017 crt->base.pipe_mask = BIT(PIPE_A);
1082 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
|
| intel_display.h | 100 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
107 PIPE_A = 0,
126 TRANSCODER_A = PIPE_A,
|
| intel_vdsc.c | 358 (pipe != PIPE_A ||
382 WARN_ON(crtc->pipe == PIPE_A);
492 if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A)
|
| intel_display_power.c | 39 return "PIPE_A";
1120 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
1121 i830_enable_pipe(dev_priv, PIPE_A);
1130 i830_disable_pipe(dev_priv, PIPE_A);
1136 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
1277 if (pipe != PIPE_A)
1501 pipe = PIPE_A;
1561 assert_pll_disabled(dev_priv, PIPE_A);
1585 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1708 enum pipe pipe = PIPE_A;
[all...] |
| intel_display.c | 1475 if (pipe != PIPE_A) {
1578 if (pipe != PIPE_A)
1595 if (pipe != PIPE_A)
1716 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1718 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1724 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1784 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1786 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1794 return PIPE_A;
2720 crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
[all...] |
| intel_dp.c | 835 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
889 pipe = PIPE_A;
965 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
3255 *pipe = PIPE_A;
3657 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
4268 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4269 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4273 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4282 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4283 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true)
[all...] |
| intel_hdmi.c | 2038 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2039 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2042 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
2056 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
2057 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2058 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3303 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
|
| intel_sdvo.c | 1757 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1758 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1761 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1767 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1768 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1769 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
|
| icl_dsi.c | 764 case PIPE_A:
1454 *pipe = PIPE_A;
|
| vlv_dsi.c | 1020 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1877 intel_encoder->pipe_mask = BIT(PIPE_A);
|
| intel_display_types.h | 1417 case PIPE_A:
|
