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Searched refs:RB_BLKSZ (Results 1 - 19 of 19) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c	`858 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1038 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1252 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);`
amdgpu_uvd_v5_0.c	`400 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);`
amdgpu_vcn_v1_0.c	`909 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1067 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);`
amdgpu_vcn_v2_0.c	`845 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1006 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);`
amdgpu_uvd_v6_0.c	`818 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);`
amdgpu_gfx_v10_0.c	`2792 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2833 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 3037 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);`
amdgpu_uvd_v7_0.c	`1070 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);`
sid.h	`1279 #define RB_BLKSZ(x) ((x) << 8)`
amdgpu_gfx_v8_0.c	`4283 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);`
amdgpu_gfx_v9_0.c	`3193 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);`
/src/sys/external/bsd/drm2/dist/drm/radeon/
rv770d.h	`353 #define RB_BLKSZ(x) ((x) << 8)`
nid.h	`488 #define RB_BLKSZ(x) ((x) << 8)`
cikd.h	`1306 #define RB_BLKSZ(x) ((x) << 8)`
sid.h	`1250 #define RB_BLKSZ(x) ((x) << 8)`
evergreend.h	`480 #define RB_BLKSZ(x) ((x) << 8)`
r600d.h	`199 #define RB_BLKSZ(x) ((x) << 8)`
radeon_rv770.c	`1110 RB_NO_UPDATE \| RB_BLKSZ(15) \| RB_BUFSZ(3));`
radeon_r600.c	`2690 RB_NO_UPDATE \| RB_BLKSZ(15) \| RB_BUFSZ(3));`
radeon_evergreen.c	`2983 RB_NO_UPDATE \| RB_BLKSZ(15) \| RB_BUFSZ(3));`

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