| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_vcn_v2_5.c | 760 uint32_t rb_bufsz, tmp; local in function:vcn_v2_5_start_dpg_mode
856 rb_bufsz = order_base_2(ring->ring_size);
857 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
892 uint32_t rb_bufsz, tmp; local in function:vcn_v2_5_start
1036 rb_bufsz = order_base_2(ring->ring_size);
1037 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1133 uint32_t offset, size, tmp, i, rb_bufsz; local in function:vcn_v2_5_sriov_start
1250 rb_bufsz = order_base_2(ring->ring_size)
[all...] |
| amdgpu_uvd_v5_0.c | 300 uint32_t rb_bufsz, tmp; local in function:uvd_v5_0_start
397 rb_bufsz = order_base_2(ring->ring_size);
399 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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| amdgpu_uvd_v7_0.c | 902 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
940 uint32_t rb_bufsz, tmp; local in function:uvd_v7_0_start
1068 rb_bufsz = order_base_2(ring->ring_size);
1069 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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| amdgpu_vcn_v1_0.c | 788 uint32_t rb_bufsz, tmp; local in function:vcn_v1_0_start_spg_mode
907 rb_bufsz = order_base_2(ring->ring_size);
908 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
962 uint32_t rb_bufsz, tmp; local in function:vcn_v1_0_start_dpg_mode
1065 rb_bufsz = order_base_2(ring->ring_size);
1066 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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| amdgpu_vcn_v2_0.c | 753 uint32_t rb_bufsz, tmp; local in function:vcn_v2_0_start_dpg_mode
843 rb_bufsz = order_base_2(ring->ring_size);
844 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
879 uint32_t rb_bufsz, tmp; local in function:vcn_v2_0_start
1004 rb_bufsz = order_base_2(ring->ring_size);
1005 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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| amdgpu_uvd_v6_0.c | 707 uint32_t rb_bufsz, tmp; local in function:uvd_v6_0_start
816 rb_bufsz = order_base_2(ring->ring_size);
817 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
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| amdgpu_gfx_v10_0.c | 2774 u32 rb_bufsz; local in function:gfx_v10_0_cp_gfx_resume
2790 rb_bufsz = order_base_2(ring->ring_size / 8);
2791 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2792 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2831 rb_bufsz = order_base_2(ring->ring_size / 8);
2832 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2833 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2984 uint32_t rb_bufsz; local in function:gfx_v10_0_gfx_mqd_init
[all...] |
| sid.h | 1278 #define RB_BUFSZ(x) ((x) << 0)
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| amdgpu_gfx_v8_0.c | 4270 u32 rb_bufsz; local in function:gfx_v8_0_cp_gfx_resume
4281 rb_bufsz = order_base_2(ring->ring_size / 8);
4282 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4283 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
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| amdgpu_gfx_v9_0.c | 3180 u32 rb_bufsz; local in function:gfx_v9_0_cp_gfx_resume
3191 rb_bufsz = order_base_2(ring->ring_size / 8);
3192 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3193 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| rv770d.h | 352 #define RB_BUFSZ(x) ((x) << 0)
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| nid.h | 487 #define RB_BUFSZ(x) ((x) << 0)
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| cikd.h | 1305 #define RB_BUFSZ(x) ((x) << 0)
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| sid.h | 1249 #define RB_BUFSZ(x) ((x) << 0)
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| evergreend.h | 479 #define RB_BUFSZ(x) ((x) << 0)
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| r600d.h | 198 #define RB_BUFSZ(x) ((x) << 0)
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| radeon_rv770.c | 1110 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
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| radeon_r600.c | 2690 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2752 u32 rb_bufsz; local in function:r600_cp_resume
2762 rb_bufsz = order_base_2(ring->ring_size / 8);
2763 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2814 u32 rb_bufsz; local in function:r600_ring_init
2818 rb_bufsz = order_base_2(ring_size / 8);
2819 ring_size = (1 << (rb_bufsz + 1)) * 4;
3504 u32 rb_bufsz; local in function:r600_ih_ring_init
3507 rb_bufsz = order_base_2(ring_size / 4);
3508 ring_size = (1 << rb_bufsz) * 4
3710 int rb_bufsz; local in function:r600_irq_init
[all...] |
| radeon_evergreen.c | 2983 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
3072 u32 rb_bufsz; local in function:evergreen_cp_resume
3088 rb_bufsz = order_base_2(ring->ring_size / 8);
3089 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
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