| /src/sys/arch/sh3/sh3/ |
| devreg.c | 103 SH ## x ## REG(TRA); \
104 SH ## x ## REG(EXPEVT); \
105 SH ## x ## REG(INTEVT); \
107 SH ## x ## REG(BARA); \
108 SH ## x ## REG(BAMRA); \
109 SH ## x ## REG(BASRA); \
110 SH ## x ## REG(BBRA); \
111 SH ## x ## REG(BARB); \
112 SH ## x ## REG(BAMRB); \
113 SH ## x ## REG(BASRB);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/ |
| amdgpu_hw_translate_dce120.c | 56 #define REG(reg_name)\
74 case REG(DC_GPIO_GENERIC_A):
104 case REG(DC_GPIO_HPD_A):
131 case REG(DC_GPIO_SYNCA_A):
145 /* REG(DC_GPIO_GENLK_MASK */
146 case REG(DC_GPIO_GENLK_A):
170 case REG(DC_GPIO_DDC1_A):
173 case REG(DC_GPIO_DDC2_A):
176 case REG(DC_GPIO_DDC3_A):
179 case REG(DC_GPIO_DDC4_A)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/ |
| amdgpu_hw_translate_dcn10.c | 56 #define REG(reg_name)\
74 case REG(DC_GPIO_GENERIC_A):
104 case REG(DC_GPIO_HPD_A):
131 case REG(DC_GPIO_SYNCA_A):
145 /* REG(DC_GPIO_GENLK_MASK */
146 case REG(DC_GPIO_GENLK_A):
170 case REG(DC_GPIO_DDC1_A):
173 case REG(DC_GPIO_DDC2_A):
176 case REG(DC_GPIO_DDC3_A):
179 case REG(DC_GPIO_DDC4_A)
[all...] |
| /src/sys/arch/luna68k/stand/boot/ |
| sio.c | 107 int rr0 = sioreg(REG(unit, RR0), 0);
108 int rr1 = sioreg(REG(unit, RR1), 0);
116 sioreg(REG(unit, WR0), WR0_ERRRST);
191 while ((sioreg(REG(unit, RR0), 0) & RR0_TXEMPTY) == 0)
197 while ((sioreg(REG(unit, RR0), 0) & RR0_TXEMPTY) == 0)
216 sioreg(REG(0, WR0), WR0_CHANRST);
224 sioreg(REG(0, WR0), WR0_RSTINT);
226 sioreg(REG(0, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY);
228 sioreg(REG(0, WR3), WR3_RX8BIT | WR3_RXENBL);
230 sioreg(REG(0, WR5), WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/ |
| amdgpu_hw_translate_dcn20.c | 59 #undef REG
60 #define REG(reg_name)\
78 case REG(DC_GPIO_GENERIC_A):
108 case REG(DC_GPIO_HPD_A):
134 /* REG(DC_GPIO_GENLK_MASK */
135 case REG(DC_GPIO_GENLK_A):
159 case REG(DC_GPIO_DDC1_A):
162 case REG(DC_GPIO_DDC2_A):
165 case REG(DC_GPIO_DDC3_A):
168 case REG(DC_GPIO_DDC4_A)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/ |
| amdgpu_hw_translate_dcn21.c | 59 #undef REG
60 #define REG(reg_name)\
77 case REG(DC_GPIO_GENERIC_A):
111 case REG(DC_GPIO_HPD_A):
137 /* REG(DC_GPIO_GENLK_MASK */
138 case REG(DC_GPIO_GENLK_A):
162 case REG(DC_GPIO_DDC1_A):
165 case REG(DC_GPIO_DDC2_A):
168 case REG(DC_GPIO_DDC3_A):
171 case REG(DC_GPIO_DDC4_A)
[all...] |
| /src/usr.sbin/gspa/gspa/ |
| gsp_inst.c | 63 #define ONEREG 1 /* reg */
64 #define TWOREG 2 /* reg, reg */
65 #define DYADIC 3 /* immediate or reg, reg */
71 #define IMMREG 4 /* immediate, reg */
75 #define KREG 5 /* short immediate, reg */
79 #define CALL 6 /* reg or address */
81 #define CLR 8 /* reg appears twice in encoding */
99 #define EXREG (REG|EXPR
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp_cm.c | 47 #define REG(reg)\
48 dpp->tf_regs->reg
130 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
131 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
140 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
141 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
150 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
151 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
225 gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12)
[all...] |
| /src/sys/arch/arm/amlogic/ |
| meson8b_pinctrl.c | 50 #define REG 0x00
168 .reg = CBUS_REG((_gpiobase) + 0), \
173 .reg = CBUS_REG((_gpiobase) + 1), \
178 .reg = CBUS_REG((_gpiobase) + 2), \
183 .reg = CBUS_REG(_pullbase), \
188 .reg = CBUS_REG(_pullbase), \
284 .reg = 0, \
289 .reg = 0, \
294 .reg = 4, \
299 .reg = 0,
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_mpc.c | 38 #define REG(reg)\
39 mpc20->mpc_regs->reg
176 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
177 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
179 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);
180 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);
235 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]);
236 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]);
238 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id])
[all...] |
| amdgpu_dcn20_dpp_cm.c | 41 #define REG(reg)\
42 dpp->tf_regs->reg
188 /* value stored in dbg reg will be 1 greater than mode we want */
200 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
201 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
203 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);
204 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);
296 icsc_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);
297 icsc_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34)
[all...] |
| amdgpu_dcn20_hubbub.c | 36 #define REG(reg)\
37 hubbub1->regs->reg
46 #define REG(reg)\
47 hubbub1->regs->reg
414 if (REG(DCN_VM_FB_LOCATION_TOP) == 0)
496 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A))
498 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
507 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| ddc_regs.h | 37 .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\
51 .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
55 .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\
56 .phy_aux_cntl = REG(PHY_AUX_CNTL), \
57 .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
60 .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\
77 .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\
96 .phy_aux_cntl = REG(PHY_AUX_CNTL), \
97 .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
|
| generic_regs.h | 34 .type ## _reg = REG(DC_GPIO_GENERIC_## type),\
48 .mux = REG(DC_GENERIC ## id),\
|
| /src/sys/dev/tc/ |
| sfbplus.c | 73 #define REG(base, index) *((uint32_t *)(base) + (index))
75 REG(vdac, bt_lo) = ((regno) & 0x00ff); \
76 REG(vdac, bt_hi) = ((regno) & 0x0f00) >> 8; \
611 REG(vdac, bt_reg) = 0x40; /* CMD0 */ tc_wmb();
612 REG(vdac, bt_reg) = 0x0; /* CMD1 */ tc_wmb();
613 REG(vdac, bt_reg) = 0xc0; /* CMD2 */ tc_wmb();
614 REG(vdac, bt_reg) = 0xff; /* PRM */ tc_wmb();
615 REG(vdac, bt_reg) = 0; /* 205 */ tc_wmb();
616 REG(vdac, bt_reg) = 0x0; /* PBM */ tc_wmb();
617 REG(vdac, bt_reg) = 0; /* 207 */ tc_wmb()
[all...] |
| stic.c | 117 #define REG(base, index) *((volatile uint32_t *)(base) + (index))
119 REG(vdac, bt_lo) = DUPBYTE0(regno); \
120 REG(vdac, bt_hi) = DUPBYTE1(regno); \
287 REG(vdac, bt_reg) = 0x00c0c0c0; tc_wmb();
296 REG(vdac, bt_reg) = 0x00000000; tc_wmb();
297 REG(vdac, bt_reg) = 0x00c2c2c2; tc_wmb();
298 REG(vdac, bt_reg) = 0x00ffffff; tc_wmb();
301 REG(vdac, bt_reg) = 0x00000000;
307 REG(vdac, bt_reg) = 0x00ffffff; tc_wmb();
308 REG(vdac, bt_reg) = 0x00ffffff; tc_wmb()
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_hwseq.c | 38 #define REG(reg)\
39 hws->regs->reg
116 if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
136 if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
144 if (REG(DCFEV_CLOCK_CONTROL))
196 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
|
| amdgpu_dce_stream_encoder.c | 42 #define REG(reg)\
43 (enc110->regs->reg)
82 if (REG(AFMT_CNTL))
85 if (REG(AFMT_VBI_PACKET_CONTROL1)) {
139 if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
146 if (REG(AFMT_VBI_PACKET_CONTROL1)) {
241 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
248 if (REG(HDMI_GENERIC_PACKET_CONTROL2))
255 if (REG(HDMI_GENERIC_PACKET_CONTROL3)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| dmub_reg.h | 45 #define REG(reg) (REGS)->offset.reg
53 #define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))
55 #define REG_WRITE(reg, val) \
56 ((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
61 dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__
[all...] |
| /src/sys/arch/amd64/include/ |
| mcontext.h | 42 #define GREG_OFFSETS(reg, REG, idx) _REG_##REG = idx,
|
| frame.h | 86 #define tf(reg, REG, idx) uint64_t tf_##reg;
|
| /src/sys/arch/vax/vsa/ |
| dz_vsbus.c | 76 #define REG(name) short name; short X##name##X;
78 REG(csr); /* 00 Csr: control/status register */
79 REG(rbuf); /* 04 Rbuf/Lpr: receive buffer/line param reg. */
80 REG(tcr); /* 08 Tcr: transmit console register */
81 REG(tdr); /* 0C Msr/Tdr: modem status reg/transmit data reg */
82 REG(lpr0); /* 10 Lpr0: */
83 REG(lpr1); /* 14 Lpr0: *
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_lrc.c | 552 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))
618 REG(0x034),
619 REG(0x030),
620 REG(0x038),
621 REG(0x03c),
622 REG(0x168),
623 REG(0x140),
624 REG(0x110),
625 REG(0x11c),
626 REG(0x114)
3185 i915_reg_t reg; member in struct:lri
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
| amdgpu_bios_parser_helper.c | 55 #define REG(reg)\
56 (bios->regs->reg)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 38 * REG ==> macro to location of register offset
39 * eg. aud110->regs->reg
42 dm_read_reg(CTX, REG(reg_name))
45 dm_write_reg(CTX, REG(reg_name), value)
58 REG(reg_name), \
69 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \
70 REG_SET_N(reg, 2, init_value, \
71 FN(reg, f1), v1,\
72 FN(reg, f2), v2)
74 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3)
[all...] |
