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    Searched refs:REG_GET_FIELD (Results 1 - 25 of 40) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfxhub_v1_1.c 40 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
64 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
67 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
amdgpu_umc_v6_1.c 81 return REG_GET_FIELD(rsmu_umc_index,
127 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
138 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
146 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
147 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
148 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
171 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
172 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
173 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
174 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 |
    [all...]
amdgpu_smu_v11_0_i2c.c 149 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0);
157 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) {
162 if (REG_GET_FIELD(reg_c_tx_abrt_source,
168 } else if (REG_GET_FIELD(reg_c_tx_abrt_source,
192 if (REG_GET_FIELD(reg_c_tx_abrt_source,
210 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0);
260 if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
287 } while (numbytes && REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF));
386 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT);
433 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &
    [all...]
amdgpu_nbio_v7_4.c 328 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
356 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
496 corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr);
497 fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
498 non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
517 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
amdgpu_gmc_v7_0.c 102 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
208 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
231 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
237 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
338 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
344 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
785 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
786 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
792 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
797 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS
    [all...]
amdgpu_amdkfd_gfx_v10.c 50 /* Because of REG_GET_FIELD() being used, we put this function in the
60 /* TODO - confirm REG_GET_FIELD x2, should be OK as is... but
65 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
67 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
308 2 << REG_GET_FIELD(m->cp_hqd_pq_control,
617 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
621 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
622 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
629 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
amdgpu_amdkfd_gfx_v7.c 92 /* Because of REG_GET_FIELD() being used, we put this function in the
101 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
103 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
487 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
491 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
492 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
499 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
717 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
amdgpu_gfx_v9_4.c 716 sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT);
723 ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT);
735 sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,
743 ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,
756 sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT);
763 ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT);
775 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,
783 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,
796 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,
804 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL
    [all...]
amdgpu_amdkfd_gfx_v8.c 49 /* Because of REG_GET_FIELD() being used, we put this function in the
58 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
60 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
485 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
489 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
490 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
497 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
amdgpu_df_v3_6.c 295 adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp,
298 adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp,
301 adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp,
717 if (REG_GET_FIELD(base_addr_reg_val,
724 base_addr = REG_GET_FIELD(base_addr_reg_val,
741 xgmi_node_id = REG_GET_FIELD(xgmi_node_id,
amdgpu_cz_ih.c 201 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
341 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
356 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
amdgpu_iceland_ih.c 201 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
341 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
356 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
amdgpu_tonga_ih.c 203 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
352 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
367 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
amdgpu_gmc_v8_0.c 190 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
333 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
356 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
362 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
540 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
546 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
1023 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
1024 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1030 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1035 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS
    [all...]
amdgpu_gmc_v10_0.c 179 REG_GET_FIELD(status,
182 REG_GET_FIELD(status,
185 REG_GET_FIELD(status,
188 REG_GET_FIELD(status,
191 REG_GET_FIELD(status,
746 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
754 size = (REG_GET_FIELD(viewport,
756 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
amdgpu_gmc_v6_0.c 87 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
637 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
638 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
643 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
648 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
827 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
831 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
832 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
amdgpu_gmc_v9_0.c 371 REG_GET_FIELD(status,
374 REG_GET_FIELD(status,
377 REG_GET_FIELD(status,
380 REG_GET_FIELD(status,
383 REG_GET_FIELD(status,
1046 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1055 size = (REG_GET_FIELD(viewport,
1057 REG_GET_FIELD(viewport,
1066 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1067 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH)
    [all...]
amdgpu_gfx_v8_0.c 1836 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1837 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1840 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1841 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1860 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
3458 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
4861 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
4973 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4977 if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
4978 REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) |
    [all...]
amdgpu_vi.c 343 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
347 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
466 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
469 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
1054 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1055 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1084 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
amdgpu_navi10_ih.c 221 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
226 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
amdgpu_gfx_v10_0.c 1219 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1226 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1229 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1232 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1235 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1728 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1729 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
2217 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2254 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2291 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL
    [all...]
amdgpu_vega10_ih.c 387 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
402 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
amdgpu_soc15.c 880 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
881 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
929 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
930 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega10_thermal.c 111 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
139 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
142 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
273 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
amdgpu_vega20_thermal.c 155 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

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