| /src/sys/arch/arm/rockchip/ |
| rk3288_cru.c | 286 RK_GATE(RK3288_ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLKGATE_CON(0), 3),
287 RK_GATE(0, "gpll_aclk_cpu", "gpll", CLKGATE_CON(0), 10),
288 RK_GATE(0, "cpll_aclk_cpu", "cpll", CLKGATE_CON(0), 11),
289 RK_GATE(RK3288_ACLK_PERI, "aclk_peri", "aclk_peri_src", CLKGATE_CON(2), 1),
290 RK_GATE(RK3288_SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", CLKGATE_CON(5), 0),
291 RK_GATE(RK3288_SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", CLKGATE_CON(5), 1),
292 RK_GATE(RK3288_SCLK_MACREF, "sclk_macref", "mac_clk", CLKGATE_CON(5), 2),
293 RK_GATE(RK3288_SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", CLKGATE_CON(5), 3),
294 RK_GATE(RK3288_PCLK_SPI0, "pclk_spi0", "pclk_peri", CLKGATE_CON(6), 4),
295 RK_GATE(RK3288_PCLK_SPI1, "pclk_spi1", "pclk_peri", CLKGATE_CON(6), 5)
[all...] |
| rk3588_cru.c | 653 RK_GATE(RK3588_PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm",
656 RK_GATE(RK3588_CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m",
658 RK_GATE(RK3588_CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm",
667 RK_GATE(RK3588_PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm",
670 RK_GATE(RK3588_CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m",
672 RK_GATE(RK3588_CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm",
843 RK_GATE(RK3588_PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root",
845 RK_GATE(RK3588_PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root",
847 RK_GATE(RK3588_PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root",
849 RK_GATE(RK3588_PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root"
[all...] |
| rk3328_cru.c | 370 RK_GATE(0, "apll_core", "apll", CLKGATE_CON(0), 0),
371 RK_GATE(0, "dpll_core", "dpll", CLKGATE_CON(0), 1),
372 RK_GATE(0, "gpll_core", "gpll", CLKGATE_CON(0), 2),
373 RK_GATE(0, "npll_core", "npll", CLKGATE_CON(0), 12),
374 RK_GATE(0, "gpll_peri", "gpll", CLKGATE_CON(4), 0),
375 RK_GATE(0, "cpll_peri", "cpll", CLKGATE_CON(4), 1),
376 RK_GATE(0, "hdmiphy_peri", "hdmiphy", CLKGATE_CON(4), 2),
377 RK_GATE(0, "pclk_bus", "pclk_bus_pre", CLKGATE_CON(8), 3),
378 RK_GATE(0, "pclk_phy_pre", "pclk_bus_pre", CLKGATE_CON(8), 4),
379 RK_GATE(RK3328_ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLKGATE_CON(10), 0)
[all...] |
| rk3399_cru.c | 439 RK_GATE(0, "clk_core_l_lpll_src", "lpll", CLKGATE_CON(0), 0),
440 RK_GATE(0, "clk_core_l_bpll_src", "bpll", CLKGATE_CON(0), 1),
441 RK_GATE(0, "clk_core_l_dpll_src", "dpll", CLKGATE_CON(0), 2),
442 RK_GATE(0, "clk_core_l_gpll_src", "gpll", CLKGATE_CON(0), 3),
451 RK_GATE(0, "clk_core_b_lpll_src", "lpll", CLKGATE_CON(1), 0),
452 RK_GATE(0, "clk_core_b_bpll_src", "bpll", CLKGATE_CON(1), 1),
453 RK_GATE(0, "clk_core_b_dpll_src", "dpll", CLKGATE_CON(1), 2),
454 RK_GATE(0, "clk_core_b_gpll_src", "gpll", CLKGATE_CON(1), 3),
466 RK_GATE(0, "gpll_aclk_perilp0_src", "gpll", CLKGATE_CON(7), 0),
467 RK_GATE(0, "cpll_aclk_perilp0_src", "cpll", CLKGATE_CON(7), 1)
[all...] |
| rk3399_pmucru.c | 317 RK_GATE(RK3399_PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLKGATE_CON(1), 0),
318 RK_GATE(RK3399_PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", CLKGATE_CON(1), 3),
319 RK_GATE(RK3399_PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", CLKGATE_CON(1), 4),
320 RK_GATE(RK3399_PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", CLKGATE_CON(1), 7),
321 RK_GATE(RK3399_PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", CLKGATE_CON(1), 8),
322 RK_GATE(RK3399_PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", CLKGATE_CON(1), 9),
323 RK_GATE(RK3399_PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", CLKGATE_CON(1), 10),
|
| rk_cru.h | 355 #define RK_GATE(_id, _name, _pname, _reg, _bit) \
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