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    Searched refs:RREG32_SMC (Results 1 - 25 of 26) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ci_smc.c 121 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
129 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
144 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
153 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
162 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
163 u32 pc_c = RREG32_SMC(SMC_PC_C);
181 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
radeon_si_smc.c 120 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
136 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
150 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
159 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
168 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
169 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
207 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
radeon_trinity_dpm.c 383 value = RREG32_SMC(GFX_POWER_GATING_CNTL);
511 if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK)
512 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01));
527 value = RREG32_SMC(PM_I_CNTL_1);
532 value = RREG32_SMC(SMU_S_PG_CNTL);
537 value = RREG32_SMC(SMU_S_PG_CNTL);
541 value = RREG32_SMC(PM_I_CNTL_1);
601 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
611 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);
623 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix)
    [all...]
radeon_ci_dpm.c 588 data = RREG32_SMC(config_regs->offset);
890 tmp = RREG32_SMC(CG_THERMAL_INT);
898 tmp = RREG32_SMC(CG_THERMAL_CTRL);
913 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
945 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
947 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
952 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
956 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
977 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1021 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT
    [all...]
radeon_kv_smc.c 65 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0);
radeon_kv_dpm.c 304 data = RREG32_SMC(config_regs->offset);
651 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
666 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
676 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
1182 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL);
2448 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1);
2475 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);
2814 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>
2823 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2838 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >
    [all...]
radeon_cik.c 223 temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
240 temp = RREG32_SMC(0xC0300E0C);
1726 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)
1729 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)
9502 tmp = RREG32_SMC(cntl_reg);
9508 if (RREG32_SMC(status_reg) & DCLK_STATUS)
9542 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
9549 tmp = RREG32_SMC(CG_ECLK_CNTL);
9555 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
9847 orig = data = RREG32_SMC(THM_CLK_CNTL)
    [all...]
radeon.h 2607 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2639 uint32_t tmp_ = RREG32_SMC(reg); \
radeon_ni.c 889 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
radeon_si.c 7507 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si_smc.c 118 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
134 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) |
148 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
160 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
161 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
199 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
amdgpu_vi.c 342 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
346 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
397 rom_cntl = RREG32_SMC(ixROM_CNTL);
803 tmp = RREG32_SMC(cntl_reg);
814 tmp = RREG32_SMC(status_reg);
890 if (RREG32_SMC(reg_status) & status_mask)
898 tmp = RREG32_SMC(reg_ctrl);
904 if (RREG32_SMC(reg_status) & status_mask)
967 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1082 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0)
    [all...]
amdgpu_kv_smc.c 68 *enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0);
amdgpu_cik.c 853 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK)
856 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK)
913 rom_cntl = RREG32_SMC(ixROM_CNTL);
1396 tmp = RREG32_SMC(cntl_reg);
1403 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
1438 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
1445 tmp = RREG32_SMC(ixCG_ECLK_CNTL);
1452 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
1754 orig = data = RREG32_SMC(ixTHM_CLK_CNTL);
1762 orig = data = RREG32_SMC(ixMISC_CLK_CTRL)
    [all...]
amdgpu_vce_v3_0.c 378 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
382 tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &
819 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
821 data = RREG32_SMC(ixCURRENT_PG_STATUS);
amdgpu_kv_dpm.c 431 data = RREG32_SMC(config_regs->offset);
732 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
747 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
758 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
2513 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1);
2542 tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
2877 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
2887 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
2963 temp = RREG32_SMC(0xC0300E0C);
3157 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL)
    [all...]
amdgpu_uvd_v4_2.c 705 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &
716 if (RREG32_SMC(ixCURRENT_PG_STATUS) &
amdgpu_uvd_v6_0.c 373 (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
1481 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1483 data = RREG32_SMC(ixCURRENT_PG_STATUS);
amdgpu_cgs.c 75 return RREG32_SMC(index);
amdgpu_uvd_v5_0.c 821 if (RREG32_SMC(ixCURRENT_PG_STATUS) &
amdgpu_debugfs.c 461 value = RREG32_SMC(*pos);
amdgpu_vce_v4_0.c 883 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
amdgpu.h 1068 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
amdgpu_uvd_v7_0.c 1687 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
amdgpu_si_dpm.c 2856 data = RREG32_SMC(offset);
7522 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7527 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7539 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7544 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);

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