| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_df_v1_7.c | 54 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
66 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
91 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
96 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
112 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
|
| amdgpu_gfxhub_v1_1.c | 38 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
68 RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
|
| amdgpu_athub_v1_0.c | 42 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
58 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
101 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
|
| amdgpu_athub_v2_0.c | 45 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
62 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
101 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
|
| amdgpu_smu_v11_0_i2c.c | 60 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);
79 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR);
147 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
155 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT);
158 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
189 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
208 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
259 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
285 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
385 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD)
[all...] |
| amdgpu_mmhub_v2_0.c | 100 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
111 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
131 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
144 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
171 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
291 tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
298 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
313 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
376 def = data = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
378 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2)
[all...] |
| amdgpu_vcn_v1_0.c | 240 RREG32_SOC15(VCN, 0, mmUVD_STATUS))
449 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
460 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
465 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
475 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
498 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
522 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
549 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
576 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
585 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE)
[all...] |
| amdgpu_jpeg_v2_5.c | 69 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING);
207 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
262 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
272 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
280 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
292 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
350 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);
398 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR);
415 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR);
446 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS)
[all...] |
| amdgpu_vega10_ih.c | 54 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
69 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
85 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
110 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
130 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
150 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
241 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
257 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
287 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
317 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2)
[all...] |
| amdgpu_navi10_ih.c | 52 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
69 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
130 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
137 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
156 ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR);
172 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
177 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
409 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
448 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL))
|
| amdgpu_nbio_v7_4.c | 73 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
101 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
189 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
249 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
304 reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER);
327 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
355 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
380 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
416 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
|
| amdgpu_nbio_v2_3.c | 52 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
81 return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
162 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);
186 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
302 reg = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER);
|
| amdgpu_nbio_v6_1.c | 40 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
72 return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);
122 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
140 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
253 reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER);
|
| amdgpu_nbio_v7_0.c | 51 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
79 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
134 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
150 data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);
243 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
|
| amdgpu_vcn_v2_5.c | 90 harvest = RREG32_SOC15(UVD, i, mmCC_UVD_HARVESTING);
327 RREG32_SOC15(VCN, i, mmUVD_STATUS)))
546 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
555 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
581 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
605 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);
632 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
711 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
720 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
742 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL)
[all...] |
| amdgpu_gfx_v10_0.c | 1115 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1128 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1209 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1526 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1527 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1702 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
1708 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
1724 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
1725 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
1774 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0)
[all...] |
| amdgpu_gfxhub_v2_0.c | 41 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
51 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
124 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
144 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
157 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
184 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
300 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
321 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
|
| amdgpu_vcn_v2_0.c | 247 RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
459 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
468 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
491 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
515 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
542 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
617 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
626 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
649 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
701 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS)
[all...] |
| amdgpu_mmhub_v1_0.c | 44 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
45 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP);
135 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
146 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
170 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
181 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);
207 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
349 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
359 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
379 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL)
[all...] |
| amdgpu_gfxhub_v1_0.c | 40 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
129 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
150 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
161 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
188 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
315 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
338 tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_smu9_baco.c | 49 reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
63 reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
|
| amdgpu_vega20_baco.c | 55 reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
69 reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
94 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
|
| amdgpu_vega10_thermal.c | 111 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
139 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
142 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
148 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
151 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
168 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
172 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
273 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
284 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
332 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL)
[all...] |
| amdgpu_vega20_thermal.c | 100 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
103 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
155 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
166 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
209 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
226 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
263 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_smu9_smumgr.c | 81 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103);
90 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
182 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102);
184 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
|
