HomeSort by: relevance | last modified time | path
    Searched refs:SBIC_CSR_MIS_2 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/arch/sgimips/stand/common/
iris_scsi.c 274 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
275 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
309 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
371 case SBIC_CSR_MIS_2 | CMD_PHASE:
381 case SBIC_CSR_MIS_2 | STATUS_PHASE:
397 case SBIC_CSR_MIS_2 | DATA_IN_PHASE:
401 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE:
420 case SBIC_CSR_MIS_2 | MESG_IN_PHASE:
435 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE:
iris_scsireg.h 329 #define SBIC_CSR_MIS_2 0x88 /* (I) ph mis, see low bits */
  /src/sys/arch/mvme68k/dev/
sbic.c 1027 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
1028 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
1067 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
1382 case SBIC_CSR_MIS_2 | CMD_PHASE:
1392 case SBIC_CSR_MIS_2 | STATUS_PHASE:
2111 case SBIC_CSR_MIS_2 | CMD_PHASE:
2119 case SBIC_CSR_MIS_2 | STATUS_PHASE:
2157 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE:
2158 case SBIC_CSR_MIS_2 | DATA_IN_PHASE:
2256 case SBIC_CSR_MIS_2 | MESG_IN_PHASE
    [all...]
sbicreg.h 256 #define SBIC_CSR_MIS_2 0x88 /* (I) ph mis, see low bits */
  /src/sys/arch/acorn32/podulebus/
sbic.c 978 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
979 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
988 if (csr == (SBIC_CSR_MIS_2 | CMD_PHASE)) {
997 } else if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
1345 case SBIC_CSR_MIS_2 | CMD_PHASE:
1369 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE:
1370 case SBIC_CSR_MIS_2 | DATA_IN_PHASE:
1393 case SBIC_CSR_MIS_2 | STATUS_PHASE:
2043 case SBIC_CSR_MIS_2 | CMD_PHASE:
2054 case SBIC_CSR_MIS_2 | STATUS_PHASE
    [all...]
sbicreg.h 256 #define SBIC_CSR_MIS_2 0x88 /* (I) ph mis, see low bits */
  /src/sys/arch/amiga/dev/
sbic.c 1042 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE)
1043 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO);
1051 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) {
1060 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) {
1410 case SBIC_CSR_MIS_2|CMD_PHASE:
1433 case SBIC_CSR_MIS_2|DATA_OUT_PHASE:
1434 case SBIC_CSR_MIS_2|DATA_IN_PHASE:
1463 case SBIC_CSR_MIS_2|STATUS_PHASE:
2217 case SBIC_CSR_MIS_2|CMD_PHASE:
2228 case SBIC_CSR_MIS_2|STATUS_PHASE
    [all...]
sbicreg.h 256 #define SBIC_CSR_MIS_2 0x88 /* (I) ph mis, see low bits */
  /src/sys/dev/ic/
wd33c93.c 1050 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
1051 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
1090 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
1901 case SBIC_CSR_MIS_2 | CMD_PHASE:
1910 case SBIC_CSR_MIS_2 | STATUS_PHASE:
1938 case SBIC_CSR_MIS_2 | DATA_IN_PHASE:
1942 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE:
2003 case SBIC_CSR_MIS_2 | MESG_IN_PHASE:
2024 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE:
2111 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE))
    [all...]
wd33c93reg.h 303 #define SBIC_CSR_MIS_2 0x88 /* (I) ph mis, see low bits */

Completed in 21 milliseconds