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Searched refs:SDMA0_CNTL (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
cik_reg.h	`206 #define SDMA0_CNTL 0xD010`
radeon_cik_sdma.c	`319 value = RREG32(SDMA0_CNTL + reg_offset); 324 WREG32(SDMA0_CNTL + reg_offset, value);`
radeon_cik.c	6891 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 6892 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp); 6893 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 6894 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); 7076 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 7077 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 7247 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); 7248 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
cikd.h	`1962 #define SDMA0_CNTL 0xD010`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v3_0.c	`594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 605 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 607 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 1356 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1361 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1372 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1377 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);`
amdgpu_sdma_v2_4.c	`1022 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1027 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1038 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1043 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);`
amdgpu_sdma_v5_0.c	`568 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 711 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 714 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 1404 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,`
amdgpu_cik_sdma.c	`384 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 393 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,`
amdgpu_sdma_v4_0.c	`1025 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 1425 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 2013 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,`

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