| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_vce_v4_0.c | 73 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR));
75 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2));
77 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));
95 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));
97 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2));
99 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3));
121 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR),
124 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2),
127 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3),
138 RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS))
[all...] |
| mxgpu_nv.h | 40 #define NV_MAIBOX_CONTROL_TRN_OFFSET_BYTE (SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_CONTROL) * 4)
41 #define NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE (SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_CONTROL) * 4 + 1)
|
| mxgpu_ai.h | 61 #define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4
62 #define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1
|
| amdgpu_jpeg_v1_0.c | 44 ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
63 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
69 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
81 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
87 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA);
93 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL);
98 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
100 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
102 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
120 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR)
[all...] |
| amdgpu_psp_v12_0.c | 110 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
130 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
151 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
170 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
192 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
204 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
267 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
289 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
315 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
318 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64)
[all...] |
| amdgpu_amdkfd_gfx_v10.c | 139 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
140 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
163 pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid);
164 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
169 while (!(RREG32(SOC15_REG_OFFSET(
176 WREG32(SOC15_REG_OFFSET(ATHUB, 0,
183 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
204 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
218 SOC15_REG_OFFSET(SDMA0, 0,
226 SOC15_REG_OFFSET(SDMA1, 0
[all...] |
| amdgpu_amdkfd_gfx_v9.c | 135 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
136 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
163 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
166 while (!(RREG32(SOC15_REG_OFFSET(
172 WREG32(SOC15_REG_OFFSET(ATHUB, 0,
177 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
180 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid,
183 while (!(RREG32(SOC15_REG_OFFSET(
189 WREG32(SOC15_REG_OFFSET(ATHUB, 0,
194 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid
[all...] |
| amdgpu_psp_v10_0.c | 193 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
214 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
258 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
259 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
264 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
265 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
270 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
271 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
276 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
277 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA)
[all...] |
| amdgpu_umc_v6_1.c | 105 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT);
107 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT);
109 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);
113 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
115 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
117 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
162 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);
166 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
225 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT);
227 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_ADDRT0_ARCT)
[all...] |
| amdgpu_mxgpu_ai.c | 61 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
71 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
143 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
147 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),
149 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),
151 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2),
153 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3),
185 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
232 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
236 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp)
[all...] |
| amdgpu_mxgpu_nv.c | 61 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
71 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
145 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
149 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0),
151 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1),
153 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2),
155 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3),
187 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
234 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_INT_CNTL));
238 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_MAILBOX_INT_CNTL), tmp)
[all...] |
| amdgpu_psp_v3_1.c | 150 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
170 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
213 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
232 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
284 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
296 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
333 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
356 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
381 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
393 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64)
[all...] |
| amdgpu_uvd_v7_0.c | 557 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
562 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
567 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
573 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
577 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
807 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
811 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,
814 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,
817 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0);
820 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW)
[all...] |
| amdgpu_amdkfd_arcturus.c | 89 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
93 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
97 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0,
101 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0,
105 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA4, 0,
109 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA5, 0,
113 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA6, 0,
117 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA7, 0,
|
| amdgpu_nbio_v2_3.c | 88 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
89 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
111 u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
265 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ);
270 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE);
275 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
280 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
|
| amdgpu_nbio_v6_1.c | 66 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
78 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
79 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
216 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
221 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
226 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
231 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
|
| amdgpu_nbio_v7_0.c | 85 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
86 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
102 u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
255 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
260 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
265 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
270 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
|
| amdgpu_psp_v11_0.c | 257 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
384 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
406 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
418 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
476 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
479 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
515 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
520 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
545 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
591 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR)
[all...] |
| amdgpu_vcn_v2_5.c | 184 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(UVD, j, mmUVD_SCRATCH9);
186 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA0);
188 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA1);
190 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_CMD);
192 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(UVD, j, mmUVD_NO_OP);
763 WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), 1,
907 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
925 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
929 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0,
980 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0
[all...] |
| amdgpu_soc15.c | 180 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
181 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
194 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
195 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
208 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
209 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
222 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
223 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
332 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
335 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA))
[all...] |
| amdgpu_vcn_v1_0.c | 142 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
144 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
146 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
148 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
150 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
804 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
853 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
857 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
879 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
883 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0
[all...] |
| amdgpu_gfxhub_v1_0.c | 377 SOC15_REG_OFFSET(GC, 0,
380 SOC15_REG_OFFSET(GC, 0,
383 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
385 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
387 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
389 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
391 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
393 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
|
| amdgpu_gfxhub_v2_0.c | 359 SOC15_REG_OFFSET(GC, 0,
362 SOC15_REG_OFFSET(GC, 0,
365 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
367 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
369 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
371 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
373 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
375 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
|
| amdgpu_mmhub_v2_0.c | 351 SOC15_REG_OFFSET(MMHUB, 0,
354 SOC15_REG_OFFSET(MMHUB, 0,
357 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
359 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
361 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
363 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
365 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
367 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
|
| amdgpu_nbio_v7_4.c | 111 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
122 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
142 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
144 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
261 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
266 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
271 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
276 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
|
